[SI-LIST] Re: TCOmin < external buffer delay
- From: preetesh rathod <preeteshrathod@xxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 20 Oct 2005 05:48:24 +0100 (BST)
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Date: Thu, 20 Oct 2005 05:46:03 +0100 (BST)
From: preetesh rathod <preeteshrathod@xxxxxxxxxxx>
Subject: Re: [SI-LIST] TCOmin < external buffer delay
To: chengyuming_ah@xxxxxxxxxxxx
In-Reply-To: <20051020015531.45346.qmail@xxxxxxxxxxxxxxxxxxxxxxxxxxx>
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Hi,
First ensure that TCOmin is specified at some load
or it has been mentioned as Minimum Tco value
observed. It is possible that manufacturer might have
mentioned TCOmin without specifying any load.
Regards,
Preetesh Rathod
--- Yuming Cheng <chengyuming_ah@xxxxxxxxxxxx> wrote:
> Hello all,
>
> When I analyze a common clok signal. The datasheet
> gives Max TCO and Min TCO.
> According to the TCO measurement, TCO include
> Internal
> Logic delay and external buffer delay. In order to
> not
> double count the external buffer delay portion of
> Tco.
> I subtract it from TCO to get the internal logic
> delay.
> I use the IBIS model and the measurement circuit to
> measure the external buffer delay.
>
> When calculate the setup margin, I use Max Tco. The
> internal logic delay is positive.
>
> When calculate the hold margin, I use Min TCO.
> Because the external buffer delay is large than Min
> TCO. Then the internal Logic delay is negative.
>
> Do I use the negavtive Internal Logic Delay or round
> up it to zero to calculate the hold margin?
>
>
> B.R.
> Astrom
>
>
>
>
>
>
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>
>
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>
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