[SI-LIST] Re: TCOmin < external buffer delay
- From: "Beal, Weston" <weston_beal@xxxxxxxxxx>
- To: "SI freelist" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 21 Oct 2005 09:22:36 -0700
Ihsan,
Actually, the method that Andy described is NOT uncertain. If you use
the load referenced timing from simulation along with the TCO times from
the driving device data sheet you can get very good common-clock bus
timing analysis. There is still some confusion about what numbers to add
and what to subtract and where to divide the path. That's the funny
thing about timing analysis. It's just adding and subtracting like we
learned to do in elementary school, but it takes an engineer with a
college degree to understand which numbers need to be added or
subtracted at the appropriate time (pun intended). The first key to
understanding is to never break-up core timing and output buffer timing
if you can help it. Use the complete TCO.
Regards,
Weston
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Ihsan Erdin
Sent: Friday, October 21, 2005 5:12 AM
To: steve weir
Cc: a.ingraham@xxxxxxxx; SI freelist
Subject: [SI-LIST] Re: TCOmin < external buffer delay
Hi Steve,
Sorry for my empty message. Although I've always been a bit leery about
this kind of behavioral modeling that merely depends on a set of numbers
under restricted conditions, I think this whole IO buffer
standardization should cover these issues as well. If not, we should
restrict the usage of these models to signal integrity for
overshoot/undershoot, termination requirements, etc. Timing is too
serious an issue to go with uncertainty in a digital circuit...
Ihsan
On 10/20/05, steve weir <weirsi@xxxxxxxxxx> wrote:
>
> Ishan, while what you say about buffer construction is true, it really
> doesn't go to Andy's point which my interpretation is:
>
> KNOW YOUR MODEL'S FRAME OF REFERENCE!
>
> One would hope that the model maker constructed the model in question=20
> such that it can be correlated to observable nodes on the board. But=20
> there isn't anything that forces them to be so reasonable.
>
> Steve.
>
> At 09:32 PM 10/20/2005 -0400, Ihsan Erdin wrote:
> >In contemporary IC devices, the buffer stage operation is distinctly=20
> >separated from that of the core logic. IO buffers are multistage=20
> >analog
> >(OPAMP) amplifiers that interface to the core logic with a=20
> >differential amplifier stage. Their output stage is a highly linear=20
> >class-AB amplifier with a low impedance to drive the load. They are=20
> >usually operated at
> higher
> >voltage levels than the core circuit because in microprocessors and=20
> >such, the internal logic has to switch at much higher rates than the=20
> >output,
> hence
> >the necessity of lower voltage levels at the core. With the advent of
> >low voltage signaling like LVDS, PECL, HSTL, etc. for gigabit=20
> >interfaces, devices that employ them have started to operate at the=20
> >same voltage as
> the
> >core but that doesn't merge the IO and core logic. In this context,=20
> >subtracting the buffer delay from the output timing is justified for=20
> >the accuracy of timing analysis.
> >As for the cases where buffer delay may be larger than the min.=20
> >output timing parameter, we know for sure that the data cannot be at=20
> >the buffer output before the min delay following the clock edge.=20
> >Rounding the
> internal
> >logic delay to zero will yield a higher than spec'd min output time,
> which
> >may mess up the whole fast process timing computations. So using the=20
> >negative number is the right thing to do.
> >
> >Ihsan Erdin
> >Nortel
> >
> >On 10/20/05, Andrew Ingraham <a.ingraham@xxxxxxxx> wrote:
> > >
> > > > According to the TCO measurement, TCO include Internal Logic=20
> > > > delay and external buffer delay.
> > >
> > > I am assuming by "external buffer" you mean the buffer, internal=20
> > > to
> your
> > > device, that drives the output (external) signal. Is that what you
> meant?
> > >
> > > > I use the IBIS model and the measurement circuit to measure the=20
> > > > external buffer delay.
> > >
> > > Be careful about this. IBIS does not necessarily model the=20
> > > external
> buffer
> > > delay. The IBIS model may represent just a portion of the buffer,=20
> > > or
> it
> > > may
> > > include more than the buffer. All you know is that IBIS describes=20
> > > how
> the
> > > buffer drives the output node. If you set up a simulation and=20
> > > measured
> the
> > > delay from the "input" of the IBIS model to its output, it is a
> relatively
> > > meaningless measurement.
> > >
> > > Aside from that, there are many reasons why the internal logic=20
> > > would appear to have a negative delay. One is if the device=20
> > > incorporates a PLL for
> the
> > > clocks. Another happens because of different loading conditions.=20
> > > If
> your
> > > calculation results in a negative number and you know you are=20
> > > doing
> the
> > > right calculations and using the right methods, then use the=20
> > > negative number, not zero.
> > >
> > > Why do you need to separate the internal logic delay from the=20
> > > output buffer, anyway? Why not just treat your device as one block
> > > that has no such boundary? (Perhaps my assumption above was=20
> > > incorrect?)
> > >
> > > Regards,
> > > Andy
> > >
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