[SI-LIST] TCOmin < external buffer delay
- From: Yuming Cheng <chengyuming_ah@xxxxxxxxxxxx>
- To: SI freelist <si-list@xxxxxxxxxxxxx>
- Date: Thu, 20 Oct 2005 09:55:31 +0800 (CST)
Hello all,
When I analyze a common clok signal. The datasheet
gives Max TCO and Min TCO.
According to the TCO measurement, TCO include Internal
Logic delay and external buffer delay. In order to not
double count the external buffer delay portion of Tco.
I subtract it from TCO to get the internal logic
delay.
I use the IBIS model and the measurement circuit to
measure the external buffer delay.
When calculate the setup margin, I use Max Tco. The
internal logic delay is positive.
When calculate the hold margin, I use Min TCO.
Because the external buffer delay is large than Min
TCO. Then the internal Logic delay is negative.
Do I use the negavtive Internal Logic Delay or round
up it to zero to calculate the hold margin?
B.R.
Astrom
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