[SI-LIST] Re: SA12E Vil and Vih
- From: "Jeremy Plunkett" <jeremy@xxxxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxxxxx, twester@xxxxxxxxxxx, mike@xxxxxxxxxxx,Andrew.Ingraham@xxxxxxxxxx
- Date: Fri, 4 Jan 2002 15:31:32 -0800
Mike,DC,Todd,Andy,
Another important question underlies Mike's original question: is it
appropriate to be using the AC Vil/Vih thresholds for a worst case timing
analysis in the first place? Many bus specifications including HSTL and
SSTL specify that all timing measurements should be taken at VREF. The AC
thresholds are specified in order to ensure enough overdrive of the input
comparator to switch at a predictable speed, and also may allow for
threshold uncertainties inherent in the receiving device such as VREF noise,
signal crosstalk, etc. However, the vendor must meet their timing in the
JEDEC specified test environment and under "actual use conditions" with the
signal crossing measured at VREF (and with the specified minimum input slew
rate).
If the engineer responsible for bus timing simulations uses the AC
thresholds for timing measurements rather then VREF, then the slow-case
simulated timing margin will be conservative by an amount equal to (AC
margin / minimum slew rate). Some extra conservatism may be desireable in
simulations, however this can add up to an unacceptably large amount of time
in many cases, such as in the DDR bus where the AC margin is 350mV and the
minimum input slew rate is 0.5v/ns for address and control signals.
The same unneccesary conservatism occurs for the fast case, where measuring
the earliest possible threshold crossing at the first AC threshold crossing
subtracts the same amount of time off of the margin compared to measuring at
VREF.
It might be convenient to measure at the AC thresholds in cases where it is
not certain whether the vendor actually does meet the specification under
worst-case conditions at the minimum slew rate, or in cases where the
simulation indicates that the minimum input slew rate may fall below the
value required by the spec, however in these cases it would be better to
address the actual issue with the vendor or board designer than simply to
"fudge" the simulations.
Another option would be to measure at some intermediate value between VREF
and the AC thresholds (say, at the DC threshold) in order to provide some
extra allowance for noise and VREF uncertainty but with less impact on the
simulated timing margins.
I am curious what the approach of other I/O designers, simulation engineers,
and spec authors is to this uncertainty--how far do you trust the
specification and the chip testing to ensure that timing measured at VREF is
accurate?
Thanks in advance for your comments,
Jeremy Plunkett
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
