Hello, Rajat, There is a lot of information on this in si-list emails in the archive. So this is just a quick summary to get you started. Take the sum of your delays: Sum for the signal path (either one chip to the next, or = latch-to-latch): (internal_chips + I/Os + pkgs + tlines + setup/hold times + jitters + = safety margin) must be less than max_allowed Some of these delays may come from simulation, others from datasheets. Delays are data-dependent; rising and falling delays are usually not = equal. Always take the biggest delay for each term. If you can afford to = simulate the entire path, your worst-case number may be faster, since there is some interaction between the various stages (particularly for = latch-to-latch simulations). * max_allowed is set by your maximum signaling rate, signaling delay = path, and setup/hold requirements at the receiver. * If your I/O timing is taken at the core_ref voltage on the core = interface pins and at VREF on the pad, you have clean timing references for the driver. * If your output is timed from the pad at VREF and your receiver pad is = timed at Vinh/Vinl, you have clean timing references for the tline delay and package delays. = If these are timed from the package pins, you need to add in the package delay = separately. * If your chip input (receiver stage) is timed from Vinh/Vinl at the = input pad to the chip's core_ref, you have clean timing through the receiver. Note = that the driving and receiving chips do not need to have the same core_ref. * Watch out for chip timing tables taken at some core_ref, while I/O = timing taken from some other voltage (from data_core to pad). This can lead to = timing errors at=20 drivers and/or receivers. * package delay: needs to include any ringing or settling time effects = due to package impedances, which in turn depends on whether on-pkg and/or on-die = terminations are=20 used. * jitter: how much jitter is tolerated (or expected) depends on things = like the=20 bit-error-rate you need and the circuit design (especially the PLL). = While jitter never has a "max" value (spikes will occur), it does have predictable = characteristics. The safety margin addresses all uncertainty in the accuracy of your = numbers. How much of a safety margin to leave, and how to adjust it for what you = know is=20 unknown, is an engineering design art. What we used 20 years ago is = useless for today's designs. The only thing I can safely say is a zero for = safety margin means there is a risk the design could work intermittently, unless all = of your other numbers are safely conservative. The best trick I ever learned was to draw a "timing diagram" showing the = transitions, and marking on each transition where the timing was measured for the = incoming and outgoing signals. This makes it easy to see where there are mismatches = in the timing definitions. do one for riding and one for falling, to keep the = picture from getting too cluttered. Best regards, Lynne -----Original Message----- From: rajat.chauhan@xxxxxx [mailto:rajat.chauhan@xxxxxx] Sent: Wednesday, January 09, 2002 10:00 PM To: Lynne Green Cc: si-list@xxxxxxxxxxxxx Subject: [SI-LIST] Re: SA12E Vil and Vih Hello Mr. Lynne, I use to face a lot of problem in specifying timings of my design. = First please tell me what do mean by "habit of leaving a 'safety=3D20' margin = ("padding") in timing allowances". Second I can't able to make out when to specify my delays in case of = output buffers, simulating my buffer alone without considering package = parasitic, or considering package parasitics, or switching 3-4 or more similar buffers = having same pow-gnd connections simultaneously, or switching 3-4 or more = similar buffers having same pow-gnd connections in some other pattern. Because in each = of the case i find different delays. Is it good to give delay range or worst = delays or any other?=20 thankyou Rajat >=20 > My I/O design experience was that designing 3.3V I/O over all > process/temperature/power supply variations did indeed lead to > receiver logic thresholds (even at DC) that were worst-case=3D20 > within ~20-30 mV of Vinh and Vinl. >=20 > Back in the good old days (about 2 years ago), the "delay" used > for chip timing analysis for I/O circuits could be assigned to = the=3D20 > "board" or the "chip" timing (and novice designers always assumed > it was done in the other one). To make matters more interesting, > board designers and I/O designers (and I/O standard cell designers) > can (and often do) use different reference voltages for their timing > simulations, leading to increased timing uncertainty. >=20 > Back then, experienced designers had the habit of leaving a = safety=3D20 > margin ("padding") in timing allowances. Unfortunately, today the > total clock cycle is >10x faster than our old rule-of-thumb padding. > Sigh... >=20 > - Lynne >=20 > "All the world's an analog stage, whereon digital plays bit parts." >=20 >=20 > Andrew.Ingraham@xxxxxxxxxx> wrote: > There are various reasons why a different edge rate causes the timings > to change. One is that the input buffer has some unpredictable input > offset voltage, so the actual "switch point" might be anywhere between > Vil and Vih (an oversimplification, perhaps, but let's use it anyway). > Another is gain bandwidth product. Even if the input buffer had no > offset voltage, its response time still depends on overdrive. >=20 > ------------------------------------------------------------------ > To unsubscribe from si-list: > si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field >=20 > or to administer your membership from a web page, go to: > //www.freelists.org/webpage/si-list >=20 > For help: > si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field >=20 > List archives are viewable at: =20 > //www.freelists.org/archives/si-list > or at our remote archives: > http://groups.yahoo.com/group/si-list/messages=20 > Old (prior to June 6, 2001) list archives are viewable at: > http://www.qsl.net/wb6tpu > =20 >=20 >=20 t'ta rajat ____________________________________________ =20 RAJAT CHAUHAN =20 STMicroelectronics Pvt. ltd. =20 (Intelligence behind Intelligence) ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu