[SI-LIST] Re: SA12E Vil and Vih
- From: rajat.chauhan@xxxxxx
- To: lgreen@xxxxxxxxxxx
- Date: Thu, 10 Jan 2002 11:29:30 +0530
Hello Mr. Lynne,
I use to face a lot of problem in specifying timings of my design. First
please tell me what do mean by "habit of leaving a 'safety=20' margin
("padding")
in timing allowances".
Second I can't able to make out when to specify my delays in case of output
buffers, simulating my buffer alone without considering package parasitic, or
considering package parasitics, or switching 3-4 or more similar buffers having
same pow-gnd connections simultaneously, or switching 3-4 or more similar
buffers
having same pow-gnd connections in some other pattern. Because in each of the
case i find different delays. Is it good to give delay range or worst delays or
any other?
thankyou
Rajat
>
> My I/O design experience was that designing 3.3V I/O over all
> process/temperature/power supply variations did indeed lead to
> receiver logic thresholds (even at DC) that were worst-case=20
> within ~20-30 mV of Vinh and Vinl.
>
> Back in the good old days (about 2 years ago), the "delay" used
> for chip timing analysis for I/O circuits could be assigned to the=20
> "board" or the "chip" timing (and novice designers always assumed
> it was done in the other one). To make matters more interesting,
> board designers and I/O designers (and I/O standard cell designers)
> can (and often do) use different reference voltages for their timing
> simulations, leading to increased timing uncertainty.
>
> Back then, experienced designers had the habit of leaving a safety=20
> margin ("padding") in timing allowances. Unfortunately, today the
> total clock cycle is >10x faster than our old rule-of-thumb padding.
> Sigh...
>
> - Lynne
>
> "All the world's an analog stage, whereon digital plays bit parts."
>
>
> Andrew.Ingraham@xxxxxxxxxx> wrote:
> There are various reasons why a different edge rate causes the timings
> to change. One is that the input buffer has some unpredictable input
> offset voltage, so the actual "switch point" might be anywhere between
> Vil and Vih (an oversimplification, perhaps, but let's use it anyway).
> Another is gain bandwidth product. Even if the input buffer had no
> offset voltage, its response time still depends on overdrive.
>
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>
t'ta
rajat
____________________________________________
RAJAT CHAUHAN
STMicroelectronics Pvt. ltd.
(Intelligence behind Intelligence)
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