Posts for si-list, 01-2002

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» [SI-LIST] Re: PC to Osilloscope communication -
» [SI-LIST] Re: rise time performance -
» [SI-LIST] Re: additional characters -
» [SI-LIST] Re: rise time performance -
» [SI-LIST] Re: Still looking for input .... -
» [SI-LIST] Re: Vintage Engineers -
» [SI-LIST] Re: additional characters -
» [SI-LIST] [Fwd: Re: Re: AC coupling placement] -
» [SI-LIST] Re: AC coupling placement -
» [SI-LIST] Re: rise time performance -
» [SI-LIST] Re: Flight time measurements and post-route analysis -
» [SI-LIST] Re: rise time performance -
» [SI-LIST] Re: rise time performance -
» [SI-LIST] Re: additional characters -
» [SI-LIST] Re: PC to Osilloscope communication -
» [SI-LIST] Re: Still looking for input .... -
» [SI-LIST] Re: PC to Osilloscope communication -
» [SI-LIST] Re: Still looking for input .... -
» [SI-LIST] Re: New Math? -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: AC coupling placement -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Still looking for input .... -
» [SI-LIST] -48V packaging references -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] additional characters -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] PC to Osilloscope communication -
» [SI-LIST] Re: Non-monotonic -
» [SI-LIST] Re: Non-monotonic -
» [SI-LIST] Obscure IBIS model info (was Common Clock and Source Synchronous Timing Margins) -
» [SI-LIST] AC coupling placement -
» [SI-LIST] Non-monotonic -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: power spectral density of random signal with finite rise/fall time -
» [SI-LIST] Re: power spectral density of random signal with finite rise/fall time -
» [SI-LIST] Re: Flight time measurements and post-route analysis -
» [SI-LIST] Re: Flight time measurements and post-route analysis -
» [SI-LIST] Flight time measurements and post-route analysis -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: Buffer Drive Strength -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: Buffer Drive Strength -
» [SI-LIST] Re: Buffer Drive Strength -
» [SI-LIST] Buffer Drive Strength -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: Vintage Engineers -
» [SI-LIST] Re: Vintage Engineers -
» [SI-LIST] power spectral density of random signal with finite rise/fall time -
» [SI-LIST] Re: Vintage Engineers -
» [SI-LIST] Re: Common Clock and Source Synchronous TimingMargins -
» [SI-LIST] Re: Common Clock and Source SynchronousTimingMargins -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Vintage Engineers -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] CLK Input not 3.3V tolerant -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: CLK Input not 3.3V tolerant -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] HSDD: Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: CLK Input not 3.3V tolerant -
» [SI-LIST] Re: CLK Input not 3.3V tolerant -
» [SI-LIST] Re: local and global ground -
» [SI-LIST] Re: local and global ground -
» [SI-LIST] CLK Input not 3.3V tolerant -
» [SI-LIST] Re: local and global ground -
» [SI-LIST] Re: local and global ground -
» [SI-LIST] Re: local and global ground -
» [SI-LIST] Re: rise time performance -
» [SI-LIST] Re: local and global ground -
» [SI-LIST] Re: local and global ground -
» [SI-LIST] Re: local and global ground -
» [SI-LIST] Re: SI Position Open READ THIS!!!! -
» [SI-LIST] local and global ground -
» [SI-LIST] [SI-LIST]: Pull-up resistor value -
» [SI-LIST] Re: rise time performance -
» [SI-LIST] Re: Common Clock and Source Synchronous Timing Margins -
» [SI-LIST] Re: Common Clock and Source Synchronous Timing Margins -
» [SI-LIST] Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: Routing a 10-bit bus on tandem grid -
» [SI-LIST] Re: Hspice B element -
» [SI-LIST] Re: Hspice B element -
» [SI-LIST] Re: Effect of vias on Ground performance -
» [SI-LIST] Re: Try to find the e-copy of manual -
» [SI-LIST] Re: Effect of vias on Ground performance -
» [SI-LIST] Re: Effect of vias on Ground performance -
» [SI-LIST] Re: Effect of vias on Ground performance -
» [SI-LIST] Re: Effect of vias on Ground performance -
» [SI-LIST] Effect of vias on Ground performance -
» [SI-LIST] Re: Common Clock and Source Synchronous Timing Margins -
» [SI-LIST] Hspice B element -
» [SI-LIST] Re: SSTL-2 differential receivers -
» [SI-LIST] Re: SSTL-2 differential receivers -
» [SI-LIST] SSTL-2 differential receivers -
» [SI-LIST] Capacitor Measurements to 10 GHz -
» [SI-LIST] Capacitor Measurements to 10 GHz -
» [SI-LIST] Re: RLGC matrix -
» [SI-LIST] Re: Common Clock and Source Synchronous Timing Margins -
» [SI-LIST] Re: BUS LVDS Spec? -
» [SI-LIST] Re: Common Clock and Source Synchronous Timing Margins -
» [SI-LIST] European IBIS Summmit - Second Announcement -
» [SI-LIST] Re: RLGC matrix -
» [SI-LIST] Re: Reference for differential Gigabit traces -
» [SI-LIST] Re: Common Clock and Source Synchronous Timing Margins -
» [SI-LIST] Re: AC Specs and SI in an MCP -
» [SI-LIST] AC Specs and SI in an MCP -
» [SI-LIST] Re: Common Clock and Source Synchronous Timing Margins -
» [SI-LIST] Reference for differential Gigabit traces -
» [SI-LIST] Re: Book -
» [SI-LIST] Re: Book -
» [SI-LIST] Book -
» [SI-LIST] Re: FW: Re: Why 50 ohms (urban legend) -
» [SI-LIST] Re: FW: Re: Why 50 ohms (urban legend) -
» [SI-LIST] RLGC matrix -
» [SI-LIST] Re: Why 50 ohms -
» [SI-LIST] Re: Why 50 ohms -
» [SI-LIST] Re: Common Clock and Source Synchronous Timing Margins -
» [SI-LIST] Try to find the e-copy of manual -
» [SI-LIST] Re: Simulating IBIS models using XTK -
» [SI-LIST] Re: Simulating IBIS models using XTK -
» [SI-LIST] Re: BUS LVDS Spec? -
» [SI-LIST] Re: 100 ohm differential GHz trace width and gap -
» [SI-LIST] Simulating IBIS models using XTK -
» [SI-LIST] Re: 100 ohm differential GHz trace width and gap -
» [SI-LIST] Re: 100 ohm differential GHz trace width and gap -
» [SI-LIST] Re: 100 ohm differential GHz trace width and gap -
» [SI-LIST] Re: Why 50 ohms -
» [SI-LIST] Re: FW: Re: Why 50 ohms -
» [SI-LIST] Re: PV/PT Tables IBIS -
» [SI-LIST] PV/PT Tables IBIS -
» [SI-LIST] Re: Why 50 ohms -
» [SI-LIST] Why 50 Ohms - Howard Johnson explains -
» [SI-LIST] FW: Re: Why 50 ohms -
» [SI-LIST] Re: About HSTL and LVDS I/Os -
» [SI-LIST] Re: Why 50 ohms -
» [SI-LIST] About HSTL and LVDS I/Os -
» [SI-LIST] Common Clock and Source Synchronous Timing Margins -
» [SI-LIST] Re: Why 50 ohms -
» [SI-LIST] Re: SA12E Vil and Vih -
» [SI-LIST] Re: Why 50 ohms -
» [SI-LIST] Why 50 ohms -
» [SI-LIST] Re: Impedance Discontinuity @ SMA connector -
» [SI-LIST] Re: IEEE CPMT inaugural meeting in Portland, OR area -
» [SI-LIST] IEEE CPMT inaugural meeting in Portland, OR area -
» [SI-LIST] Re: Signal integrity -- training in XTK simulation software -
» [SI-LIST] Re: Ground bounce issue in FPGA? -
» [SI-LIST] Re: E1/T1/E3/T3 requirements -
» [SI-LIST] Re: Ground bounce issue in FPGA? -
» [SI-LIST] Re: Ground bounce issue in FPGA? -
» [SI-LIST] Ground bounce issue in FPGA? -
» [SI-LIST] Labview Drivers for HP 71501 Jitter Analyzer / BERT -
» [SI-LIST] Re: Package Frequency? -
» [SI-LIST] Re: Package Frequency? -
» [SI-LIST] Re: Package Frequency? -
» [SI-LIST] Re: Package Frequency? -
» [SI-LIST] Re: Package Frequency? -
» [SI-LIST] Package Frequency? -
» [SI-LIST] Re: Impedance Discontinuity @ SMA connector -
» [SI-LIST] a query about HSTL I/O -
» [SI-LIST] Re: E1/T1/E3/T3 requirements -
» [SI-LIST] Package Frequency? -
» [SI-LIST] Re: Question about SSTL Termination -
» [SI-LIST] Running mks2i -
» [SI-LIST] Re: Impedance Discontinuity @ SMA connector -
» [SI-LIST] Impedance Discontinuity @ SMA connector -
» [SI-LIST] Re: E1/T1/E3/T3 requirements -
» [SI-LIST] Re: Question about SSTL Termination -
» [SI-LIST] Re: E1/T1/E3/T3 requirements -
» [SI-LIST] Re: Question about SSTL Termination -
» [SI-LIST] Question about SSTL Termination -
» [SI-LIST] Re: E1/T1/E3/T3 requirements -
» [SI-LIST] Re: E1/T1/E3/T3 requirements -
» [SI-LIST] Re: E1/T1/E3/T3 requirements -
» [SI-LIST] Re: E1/T1/E3/T3 requirements -
» [SI-LIST] Re: E1/T1/E3/T3 requirements -
» [SI-LIST] Re: E1/T1/E3/T3 requirements -
» [SI-LIST] Re: E1/T1/E3/T3 requirements -
» [SI-LIST] E1/T1/E3/T3 requirements -
» [SI-LIST] Re: Differential S-parameters -
» [SI-LIST] Re: Differential S-parameters -
» [SI-LIST] Re: Differential S-parameters -
» [SI-LIST] Re: Differential S-parameters -
» [SI-LIST] Re: Differential S-parameters -
» [SI-LIST] Re: Differential S-parameters -
» [SI-LIST] Re: hspice question - urgent -
» [SI-LIST] Re: hspice question - urgent -
» [SI-LIST] Re: hspice question - urgent -
» [SI-LIST] Re: Differential S-parameters -
» [SI-LIST] Re: Differential S-parameters -
» [SI-LIST] Re: Differential S-parameters -
» [SI-LIST] GigaTest Events: January -
» [SI-LIST] Re: BUS LVDS Spec? -
» [SI-LIST] Re: Differential S-parameters -
» [SI-LIST] BUS LVDS Spec? -
» [SI-LIST] Re: IBIS Driver Models, Simulators and CComp -
» [SI-LIST] Re: SV: Total load capacitance -
» [SI-LIST] Re: Differential S-parameters -
» [SI-LIST] Re: SV: Total load capacitance -
» [SI-LIST] Re: SV: Total load capacitance -
» [SI-LIST] Re: SA12E Vil and Vih -
» [SI-LIST] Impedance & crosstalk calculation -
» [SI-LIST] Re: Ground plane voids under Tip/Ring -
» [SI-LIST] Re: Ground plane voids under Tip/Ring -
» [SI-LIST] Re: SV: Total load capacitance -
» [SI-LIST] Re: Differential S-parameters -
» [SI-LIST] Re: SV: Total load capacitance -
» [SI-LIST] Re: IBIS Driver Models, Simulators and CComp -
» [SI-LIST] Re: Differential S-parameters -
» [SI-LIST] Re: Ground plane voids under Tip/Ring -
» [SI-LIST] Re: Ground plane voids under Tip/Ring -
» [SI-LIST] Re: Ground plane voids under Tip/Ring -
» [SI-LIST] Re: Ground plane voids under Tip/Ring -
» [SI-LIST] Re: Differential S-parameters -
» [SI-LIST] Re: Ground plane voids under Tip/Ring -
» [SI-LIST] Re: SV: Total load capacitance -
» [SI-LIST] Re: Differential S-parameters -
» [SI-LIST] Re: Use of Tenting Phenomena during Solder Masking - NEBS MFG -
» [SI-LIST] Re: Ground plane voids under Tip/Ring -
» [SI-LIST] Re: IBIS Driver Models, Simulators and CComp -
» [SI-LIST] Re: IBIS Driver Models, Simulators and CComp -
» [SI-LIST] Differential S-parameters -
» [SI-LIST] Re: IBIS Driver Models, Simulators and CComp -
» [SI-LIST] SSTL and the series resistor -
» [SI-LIST] SV: Total load capacitance -
» [SI-LIST] Re: SA12E Vil and Vih -
» [SI-LIST] SSTL and the series resistor -
» [SI-LIST] Ground plane voids under Tip/Ring -
» [SI-LIST] Re: IBIS Driver Models, Simulators and CComp -
» [SI-LIST] IBIS Driver Models, Simulators and CComp -
» [SI-LIST] Total load capacitance -
» [SI-LIST] Re: Source impedance? -
» [SI-LIST] Re: PCB Fabrication Details -
» [SI-LIST] AW: PCB Fabrication Details -
» [SI-LIST] PCB Fabrication Details -
» [SI-LIST] Re: Source impedance? -
» [SI-LIST] Re: Source impedance? -
» [SI-LIST] Re: Source impedance? -
» [SI-LIST] Re: Source impedance? -
» [SI-LIST] Re: Source impedance? -
» [SI-LIST] Re: Source impedance? -
» [SI-LIST] Re: Source impedance? -
» [SI-LIST] Re: Source impedance? -
» [SI-LIST] Source impedance? -
» [SI-LIST] Re: SA12E Vil and Vih -
» [SI-LIST] Some questions; high speed/high density -
» [SI-LIST] Re: Etch back - plating tail effect -
» [SI-LIST] Re: Use of Tenting Phenomena during Solder Masking -
» [SI-LIST] Etch back - plating tail effect -
» [SI-LIST] Re: SA12E Vil and Vih -
» [SI-LIST] IBIS European Summit Meeting Announcment 3/8/02 -
» [SI-LIST] Re: Use of Tenting Phenomena during Solder Masking -
» [SI-LIST] AW: Use of Tenting Phenomena during Solder Masking -
» [SI-LIST] Use of Tenting Phenomena during Solder Masking -
» [SI-LIST] Re: SA12E Vil and Vih -
» [SI-LIST] Re: SA12E Vil and Vih -
» [SI-LIST] Re: SA12E Vil and Vih -
» [SI-LIST] Re: SA12E Vil and Vih -
» [SI-LIST] MBS2IS -
» [SI-LIST] job postings -
» [SI-LIST] Re: Fwd: Re: LVPECL -to-LVDS translator -
» [SI-LIST] Fwd: Re: LVPECL -to-LVDS translator -
» [SI-LIST] Re: SA12E Vil and Vih -
» [SI-LIST] Buried Resistor -
» [SI-LIST] Re: Flux -
» [SI-LIST] Re: Flux -
» [SI-LIST] Re: Flux -
» [SI-LIST] Re: SA12E Vil and Vih -
» [SI-LIST] Re: SA12E Vil and Vih -
» [SI-LIST] Re: SA12E Vil and Vih -
» [SI-LIST] Re: 4 corner test -
» [SI-LIST] Re: Papers Available -
» [SI-LIST] Patterns for testing 100Base-T PHY layer -
» [SI-LIST] Re: Flux -
» [SI-LIST] Re: Flux -
» [SI-LIST] Re: SA12E Vil and Vih -
» [SI-LIST] Re: Flux -
» [SI-LIST] Flux -
» [SI-LIST] 4 corner test -
» [SI-LIST] cable induced circuit damage and corruption -
» [SI-LIST] Re: Papers Available -
» [SI-LIST] Papers Available -
» [SI-LIST] Re: SA12E Vil and Vih -
» [SI-LIST] Re: SI Engineer Qualification -
» [SI-LIST] Re: SI Engineer Qualification -
» [SI-LIST] Re: Equation -
» [SI-LIST] Re: Reflection and EMI -
» [SI-LIST] Re: SI Engineer Qualification -