[SI-LIST] Re: SA12E Vil and Vih
- From: "Ingraham, Andrew" <Andrew.Ingraham@xxxxxxxxxx>
- To: "Jeremy Plunkett" <jeremy@xxxxxxxxxxxxxxx>
- Date: Mon, 7 Jan 2002 09:18:22 -0500
Jeremy,
This is a good point, and I'm sure there are different ways of handling
it.
One problem with taking your timing measurements at VREF, is that the
component's timing specifications apply only when using some specified
input edge (slew) rate. As long as your actual input edge rate (or the
one you see in your simulations) happens to be the same as the one in
the data sheet, and the component's timing was specified at VREF, then,
theoretically, it is safe to do your system timing measurements at VREF.
Provided, of course, that you have confidence in the vendor's data and
in your work.
If the input edge rate differs from the data sheet value, whether it is
slower OR faster, then it may not be valid to measure your timings at
VREF. Since the edge rate rarely equals the data sheet value, this is
the norm.
There are various reasons why a different edge rate causes the timings
to change. One is that the input buffer has some unpredictable input
offset voltage, so the actual "switch point" might be anywhere between
Vil and Vih (an oversimplification, perhaps, but let's use it anyway).
Another is gain bandwidth product. Even if the input buffer had no
offset voltage, its response time still depends on overdrive.
One approach to handle edge rate factors, is to take your measurements
at Vil and Vih (or at Vil-X and at Vih+X, where X is some amount of
padding you wish to include to account for noise and crosstalk), and
then correlate them back to Vref using the data-sheet-specified edge
rate.
Something similar to this is done in the PCI specification.
As for the question about how to trust the chip specification in the
first place, that is a good question...
Regards,
Andy
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