Lee, Chris I worked in a board shop many years ago. My understanding of the original intention of adding thieving to signal layers was to promote consistent etching (or plating) and as a result even distribution of etch widths. The chemical process of etching inner layers is in general more consistent if there is an even distribution of copper across the panel (subtractive or additive processes - etching or plating both benefits).=20 There are numerous subtleties like etching/plating varies from center to edge of the panel and what specific type of additive or subtractive processes, chemicals, electro plating, ... you are using. =20 As folks have pointed out you must be very careful with spacing to critical signals and adjacent layer stripline pairs.=20 We had some interesting arguments at the dinner table when "Auto-thieving" was first introduces at Digital - my brother is a Chemical Engineer, my mom is a Produce-ability (Manufacturing) Engineer and I am an EE ..... Regards, Bob Haller Enterasys Networks=20 -----Original Message----- From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf of Lee Ritchey Sent: Thursday, February 23, 2006 12:31 PM To: Chris Padilla (cpad); ivorlist@xxxxxxxxxxx; Pradeep.RSA@xxxxxxxxxxxx Cc: si-list@xxxxxxxxxxxxx Subject: [SI-LIST] Re: Ground Pour in Signal Layers Chris, Of the three reasons listed below, only number 2 is of value. Shield islands don't really do that. They may induce cross talk. Fabricators don't need fill in signal layers to prevent warpage. I'm not sure where that one got started. Also, doesn't help control impedance, but rather, can make it drop if the fill is too close. Don't mean to offend anyone with these answers, but the record needs to be set straight. > [Original Message] > From: Chris Padilla (cpad) <cpad@xxxxxxxxx> > To: <ivorlist@xxxxxxxxxxx>; <Pradeep.RSA@xxxxxxxxxxxx> > Cc: <si-list@xxxxxxxxxxxxx> > Date: 2/23/2006 8:53:40 AM > Subject: [SI-LIST] Re: Ground Pour in Signal Layers > > "Ground" pour can serve several purposes: > > (1) Create shielded islands > (2) Create some extra interplane capacitance (not sure how useful it is > for charge storage as it is most likely located electrically far from > the chip needing the current) > (3) Balance out a layer to avoid warpage issues and to ensure better > trace dimension (impedance) control > > I think (3) is the big one: Fab shops often request the ability to add > "thieving" in areas of sparse metal. Some folks just go ahead and add > the metal pour and often sink several "ground" vias through it to > connect it up to something. I forget the details why, but the fab shops > have better control of trace width if they don't have to etch away a lot > of metal. > > As in all cases, such items can cause problems if not carefully handled > and thought through. > > Chris Padilla > Cisco Systems > San Jose, CA ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu