[SI-LIST] Re: Ground Pour in Signal Layers

Might want to check with the process engineers at Merix or TTM on this one.


> [Original Message]
> From: Grasso, Charles <Charles.Grasso@xxxxxxxxxxxx>
> To: <leeritchey@xxxxxxxxxxxxx>; Gerry Gagnon <mrgagman@xxxxxxxxxxx>;
<rhaller@xxxxxxxxxxxxx>
> Cc: <si-list@xxxxxxxxxxxxx>
> Date: 2/28/2006 9:34:58 AM
> Subject: RE: [SI-LIST] Re: Ground Pour in Signal Layers
>
> How interesting! I have not had to deal with thieving on inner layers
> so I popped down to our layout group and asked our folks there. The
> consensus was - YES - Thieving on inner layers can be necessary and
> should be used for unbalanced layouts. Indeed one former employee of DDI
> indicated that DDI had a program that automatically added thieving
> based
> on the design. The reason for adding the thieving is to avoid warpage.
>
>
> Best Regards
> Charles Grasso
> Senior Compliance Engineer
> Echostar Communications Corp.
> Tel: 303-706-5467
> Fax: 303-799-6222
> Cell: 303-204-2974
> Pager/Short Message: 3032042974@xxxxxxxx
> Email: charles.grasso@xxxxxxxxxxxx;
> Email Alternate: chasgrasso@xxxxxxxx
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Lee Ritchey
> Sent: Tuesday, February 28, 2006 9:44 AM
> To: Gerry Gagnon; rhaller@xxxxxxxxxxxxx
> Cc: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Ground Pour in Signal Layers
>
> Gerry,
>
> I'm not sure what length of involvement has to do with this, but if it
> is
> important, I've been at it PCB fab since 1969 and have crawled through
> perhaps 250 PCB shops all over the world, most recently in November of
> 2005.
>
> Virtually all of what I have designed and had fabricated are high speed
> PCBs and adding thieving to the inner layers has never been necessary
> and
> is not now.
>
> As to who I consider the best shops in the world, that's a subject for
> off
> line discussion as adivising clients on this matter is part of my
> specialty.
>
>
> > [Original Message]
> > From: Gerry Gagnon <mrgagman@xxxxxxxxxxx>
> > To: <leeritchey@xxxxxxxxxxxxx>; <rhaller@xxxxxxxxxxxxx>
> > Cc: <si-list@xxxxxxxxxxxxx>
> > Date: 2/27/2006 5:36:57 PM
> > Subject: [SI-LIST] Re: Ground Pour in Signal Layers
> >
> > Lee,
> >
> > Sorry but I gotta defend my old pal Rob.
> >
> > I started in PWBs back in 1978 and have been there ever since. By my
> count 
> > that's 28 years with the last 8 or so exclusively in design & supply
> chain 
> > support.
> >
> > I know of NO creditable lamination engineer tasked with gluing many
> cores 
> > together who would ever complain about getting properly theived inner
> signal 
> > layers. Theiving innerlayers provides a similar benefit to resin flow 
> > characteristices that external theiving provides to pattern plating. 
> > Especially with tight dielectric thickness tolerances, resin content 
> > tolerances, thick or different copper weights, and tight warpage
> specs. I 
> > have built many hi layer count, high speed boards using autotheiving
> on 
> > inner and outerlayers. Most could not have been done without it.
> >
> > I will say that there is minimal benefit for the lower PWB
> technologies,
> so 
> > if you design these types of products, you are getting the right
> advice.
> >
> > BTW - Having crawled through a few shops in my day (now focussed more
> on
> the 
> > Far East, India, and Eastern Europe), I'm curious as to who you
> consider
> the 
> > best fabricators in the world to be today?
> >
> > Regards,
> >
> > Gerry Gagnon
> >
> >
> >
> > ----Original Message Follows----
> > From: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
> > Reply-To: leeritchey@xxxxxxxxxxxxx
> > To: "Robert Haller" <rhaller@xxxxxxxxxxxxx>
> > CC: si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] Re: Ground Pour in Signal Layers
> > Date: Mon, 27 Feb 2006 12:13:56 -0800
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> >
> > Bob,
> >
> > If you don't mind sharing the names of those process engineers with
> us,
> I'd
> > appreciate it.  I'd like ot speak with them myself as that data flies
> > directly in the face of the advice from the best fabricators in the
> > industry.
> >
> >
> >  > [Original Message]
> >  > From: Haller, Robert <rhaller@xxxxxxxxxxxxx>
> >  > To: <leeritchey@xxxxxxxxxxxxx>
> >  > Cc: <si-list@xxxxxxxxxxxxx>
> >  > Date: 2/27/2006 11:14:07 AM
> >  > Subject: [SI-LIST] Re: Ground Pour in Signal Layers
> >  >
> >  > Lee,
> >  >  I spoke with a few process engineers and have learned something,
> >  > and felt compelled to respond to inform (I do not intent to
> offend).
> >  >
> >  > Copper pour or thieving on inner layers, I have been told by two
> >  > separate processing engineers can lead to "better lamination", and
> as
> >  > always it depends on the circuit.
> >  >
> >  > One example is if you are using very thin cores (i.e. BC) and the
> >  > circuit has large areas void of copper you may get curling. The
> final
> >  > layer stack may yield poor lamination (delamination), have
> increased
> >  > stresses and possible registration issues. =20
> >  >
> >  > PCB processes today have not changed that much (in fact they have
> >  > changed too little IMHO when compared to semiconductor advances),
> so I
> >  > would respectively disagree that the past is in fact relevant.=20
> >  >
> >  > Regards,
> >  > Bob=20
> >  >
> >  > -----Original Message-----
> >  > From: Lee Ritchey [mailto:leeritchey@xxxxxxxxxxxxx]=20
> >  > Sent: Thursday, February 23, 2006 5:41 PM
> >  > To: Haller, Robert; Chris Padilla (cpad); ivorlist@xxxxxxxxxxx;
> >  > Pradeep.RSA@xxxxxxxxxxxx
> >  > Cc: si-list@xxxxxxxxxxxxx
> >  > Subject: RE: [SI-LIST] Re: Ground Pour in Signal Layers
> >  >
> >  > Etching and plating are two very different operations.  Plating
> depends
> >  > on
> >  > uniform current distribution.  Etching is done by spraying etchant
> onto
> >  > the
> >  > surface and proceeds at the same rate over the entire surface.  All
> you
> >  > gotta do is ask a process engineer at a currently operating fab
> shop to
> >  > see
> >  > if thieving is needed on inner layers.  every time I ask, the
> answer is
> >  > no.
> >  >
> >  > What may have been at some point in the past is not relevant.  What
> is,
> >  > is
> >  > what todays' fabricators need and theiving on inner layers is not
> one
> of
> >  > them..
> >  >
> >  >
> >  > > [Original Message]
> >  > > From: Haller, Robert <rhaller@xxxxxxxxxxxxx>
> >  > > To: <leeritchey@xxxxxxxxxxxxx>; Chris Padilla (cpad)
> <cpad@xxxxxxxxx>;
> >  > <ivorlist@xxxxxxxxxxx>; <Pradeep.RSA@xxxxxxxxxxxx>
> >  > > Cc: <si-list@xxxxxxxxxxxxx>
> >  > > Date: 2/23/2006 11:54:20 AM
> >  > > Subject: [SI-LIST] Re: Ground Pour in Signal Layers
> >  > >
> >  > > Lee, Chris
> >  > >   I worked in a board shop many years ago. My understanding of
> the
> >  > > original intention of adding thieving to signal layers was to
> promote
> >  > > consistent etching (or plating) and as a result even distribution
> of
> >  > > etch widths. The chemical process of etching inner layers is in
> >  > general
> >  > > more consistent if there is an even distribution of copper across
> the
> >  > > panel (subtractive or additive processes - etching or plating
> both
> >  > > benefits).=3D20
> >  > >
> >  > > There are numerous subtleties like etching/plating varies from
> center
> >  > to
> >  > > edge of the panel and what specific type of additive or
> subtractive
> >  > > processes, chemicals, electro plating, ... you are using.
> >  > > =3D20
> >  > > As folks have pointed out you must be very careful with spacing
> to
> >  > > critical signals and adjacent layer stripline pairs.=3D20
> >  > >
> >  > > We had some interesting arguments at the dinner table when
> >  > > "Auto-thieving" was first introduces at Digital - my brother is a
> >  > > Chemical Engineer, my mom is a Produce-ability (Manufacturing)
> >  > Engineer
> >  > > and I am an EE .....
> >  > >
> >  > > Regards,
> >  > > Bob Haller
> >  > > Enterasys Networks=3D20
> >  > >
> >  > >
> >  > >
> >  > > -----Original Message-----
> >  > > From: si-list-bounce@xxxxxxxxxxxxx
> >  > [mailto:si-list-bounce@xxxxxxxxxxxxx]
> >  > > On Behalf of Lee Ritchey
> >  > > Sent: Thursday, February 23, 2006 12:31 PM
> >  > > To: Chris Padilla (cpad); ivorlist@xxxxxxxxxxx;
> >  > Pradeep.RSA@xxxxxxxxxxxx
> >  > > Cc: si-list@xxxxxxxxxxxxx
> >  > > Subject: [SI-LIST] Re: Ground Pour in Signal Layers
> >  > >
> >  > > Chris,
> >  > >
> >  > > Of the three reasons listed below, only number 2 is of value.
> Shield
> >  > > islands don't really do that.  They may induce cross talk.
> >  > Fabricators
> >  > > don't need fill in signal layers to prevent warpage.  I'm not
> sure
> >  > where
> >  > > that one got started.  Also, doesn't help control impedance, but
> >  > rather,
> >  > > can make it drop if the fill is too close.
> >  > >
> >  > > Don't mean to offend anyone with these answers, but the record
> needs
> >  > to
> >  > > be
> >  > > set straight.
> >  > >
> >  > >
> >  > > > [Original Message]
> >  > > > From: Chris Padilla (cpad) <cpad@xxxxxxxxx>
> >  > > > To: <ivorlist@xxxxxxxxxxx>; <Pradeep.RSA@xxxxxxxxxxxx>
> >  > > > Cc: <si-list@xxxxxxxxxxxxx>
> >  > > > Date: 2/23/2006 8:53:40 AM
> >  > > > Subject: [SI-LIST] Re: Ground Pour in Signal Layers
> >  > > >
> >  > > > "Ground" pour can serve several purposes:
> >  > > >
> >  > > > (1) Create shielded islands
> >  > > > (2) Create some extra interplane capacitance (not sure how
> useful
> it
> >  > > is
> >  > > > for charge storage as it is most likely located electrically
> far
> >  > from
> >  > > > the chip needing the current)
> >  > > > (3) Balance out a layer to avoid warpage issues and to ensure
> better
> >  > > > trace dimension (impedance) control
> >  > > >
> >  > > > I think (3) is the big one:  Fab shops often request the
> ability to
> >  > > add
> >  > > > "thieving" in areas of sparse metal.  Some folks just go ahead
> and
> >  > add
> >  > > > the metal pour and often sink several "ground" vias through it
> to
> >  > > > connect it up to something.  I forget the details why, but the
> fab
> >  > > shops
> >  > > > have better control of trace width if they don't have to etch
> away
> a
> >  > > lot
> >  > > > of metal.
> >  > > >
> >  > > > As in all cases, such items can cause problems if not carefully
> >  > > handled
> >  > > > and thought through.
> >  > > >
> >  > > > Chris Padilla
> >  > > > Cisco Systems
> >  > > > San Jose, CA
> >  > >
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