Posts for si-list, 02-2006

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» [SI-LIST] Re: Ground Pour in Signal Layers -
» [SI-LIST] Re: How to convert Hspice model -
» [SI-LIST] Re: How to convert Hspice model -
» [SI-LIST] Re: Ground Pour in Signal Layers -
» [SI-LIST] Re: Integrated vs. discrete magnetics for Ethernet -
» [SI-LIST] Re: Ground Pour in Signal Layers -
» [SI-LIST] Re: Ground Pour in Signal Layers -
» [SI-LIST] Re: Integrated vs. discrete magnetics for Ethernet -
» [SI-LIST] Re: Ground Pour in Signal Layers -
» [SI-LIST] Re: Ground Pour in Signal Layers -
» [SI-LIST] Re: Ground Pour in Signal Layers -
» [SI-LIST] Re: Integrated vs. discrete magnetics for Ethernet -
» [SI-LIST] Re: SATA II Electrical Specification -
» [SI-LIST] FW: RE: DDR2 design -
» [SI-LIST] Re: DDR2 design -
» [SI-LIST] Re: Integrated vs. discrete magnetics for Ethernet -
» [SI-LIST] Re: How to convert Hspice model -
» [SI-LIST] Re: Ground Pour in Signal Layers -
» [SI-LIST] How to convert Hspice model -
» [SI-LIST] Re: Why do we use transformer for DC blocking in ethernet connection ? -
» [SI-LIST] Re: Why do we use transformer for DC blocking in ethernet connection ? -
» [SI-LIST] Re: Ground Pour in Signal Layers -
» [SI-LIST] Re: Ground Pour in Signal Layers -
» [SI-LIST] Re: Macromodeling software available from Politecnico di Torino -
» [SI-LIST] Re: Integrated vs. discrete magnetics for Ethernet -
» [SI-LIST] Re: Integrated vs. discrete magnetics for Ethernet -
» [SI-LIST] European IBIS Summit at DATe 2006 - Final Call for Paper/Call for Participation -
» [SI-LIST] Integrated vs. discrete magnetics for Ethernet -
» [SI-LIST] Re: Macromodeling software available from Politecnico di Torino -
» [SI-LIST] Re: Type of Driver -
» [SI-LIST] Re: What is correctly placement of Transformer? Locate Near IC or RJ45 CONN? Why? -
» [SI-LIST] Macromodeling software available from Politecnico di Torino -
» [SI-LIST] Re: What is correctly placement of Transformer? Locate Near IC or RJ45 CONN? Why? -
» [SI-LIST] cable discharge, devices, and standards -
» [SI-LIST] What is correctly placement of Transformer? Locate Near IC or RJ45 CONN? Why? -
» [SI-LIST] Re: Why do we use transformer for DC blocking in ethernet connection ? -
» [SI-LIST] Why do we use transformer for DC blocking in ethernet connection ? -
» [SI-LIST] Re: Looking for 3D fullwave EM modeling tools -
» [SI-LIST] Re: Optimization by HSPICE of curve-fit data -
» [SI-LIST] Re: Looking for 3D fullwave EM modeling tools -
» [SI-LIST] Looking for 3D fullwave EM modeling tools -
» [SI-LIST] ICM 1.1 approved as an ANSI standard! -
» [SI-LIST] Re: Ground Pour in Signal Layers -
» [SI-LIST] Re: DDR2 design -
» [SI-LIST] Re: Ground Pour in Signal Layers -
» [SI-LIST] Re: Ground Pour in Signal Layers -
» [SI-LIST] Re: Ground Pour in Signal Layers -
» [SI-LIST] Re: Ground Pour in Signal Layers -
» [SI-LIST] Re: Ground Pour in Signal Layers -
» [SI-LIST] Re: DDR2 design -
» [SI-LIST] Re: Ground Pour in Signal Layers -
» [SI-LIST] Re: Ground Pour in Signal Layers -
» [SI-LIST] Re: DDR2 design -
» [SI-LIST] Re: DDR2 design -
» [SI-LIST] Re: Ground Pour in Signal Layers -
» [SI-LIST] Ground Pour in Signal Layers -
» [SI-LIST] Re: DDR2 design -
» [SI-LIST] Re: Can we drive 100Mhz SSTL_18 with standard ALVC or other 1.8V logic -
» [SI-LIST] Re: DDR2 design -
» [SI-LIST] Re: DDR2 design -
» [SI-LIST] Re: DDR2 design -
» [SI-LIST] Re: DDR2 design -
» [SI-LIST] Re: DDR2 design -
» [SI-LIST] Re: DDR2 design -
» [SI-LIST] Re: DDR2 design -
» [SI-LIST] Re: DDR2 design -
» [SI-LIST] Re: DDR2 design -
» [SI-LIST] DDR2 design -
» [SI-LIST] Optimization by HSPICE of curve-fit data -
» [SI-LIST] Re: Electrical wiring questions -
» [SI-LIST] optimization of curve-fit data -
» [SI-LIST] Re: Can we drive 100Mhz SSTL_18 with standard ALVC or other 1.8V logic -
» [SI-LIST] Re: Can we drive 100Mhz SSTL_18 with standard ALVC or other 1.8V logic -
» [SI-LIST] Can we drive 100Mhz SSTL_18 with standard ALVC or other 1.8V logic -
» [SI-LIST] SATA II Electrical Specification -
» [SI-LIST] Re: Electrical wiring questions -
» [SI-LIST] Re: Electrical wiring questions -
» [SI-LIST] Re: S-parameter to Circuit Model extraction? -
» [SI-LIST] Re: S-parameter to Circuit Model extraction? -
» [SI-LIST] Re: S-parameter to Circuit Model extraction? -
» [SI-LIST] Re: attached files (was Re: Digest Number 1730) -
» [SI-LIST] help request: 3D model library -
» [SI-LIST] Re: S-parameter to Circuit Model extraction? -
» [SI-LIST] Re: S-parameter to Circuit Model extraction? -
» [SI-LIST] Re: S-parameter to Circuit Model extraction? -
» [SI-LIST] S-parameter to Circuit Model extraction? -
» [SI-LIST] Re: Digest Number 1730 -
» [SI-LIST] Re: Digest Number 1730 -
» [SI-LIST] Re: Electrical wiring questions -
» [SI-LIST] Re: Electrical wiring questions -
» [SI-LIST] Re: Electrical wiring questions -
» [SI-LIST] Re: Electrical wiring questions -
» [SI-LIST] Re: currnet through wire bond: correction -
» [SI-LIST] Re: Electrical wiring questions -
» [SI-LIST] Electrical wiring questions -
» [SI-LIST] Looking for mini x12 board to cable system....... -
» [SI-LIST] SI Employment Opportunity at Altera: Posting -
» [SI-LIST] Re: DesignCon 2006 material on power distribution network design methodologies posted -
» [SI-LIST] Re: Effect of Pwr-Gnd plane pairing vs. non-paired planes on signal return currents -
» [SI-LIST] Re: Effect of Pwr-Gnd plane pairing vs. non-paired planes on signal return currents -
» [SI-LIST] FW: Re: currnet through wire bond -
» [SI-LIST] Re: HSPICE - adding jitter to ethernet serial link -
» [SI-LIST] Re: HSPICE - adding jitter to ethernet serial link -
» [SI-LIST] Re: HSPICE - adding jitter to ethernet serial link -
» [SI-LIST] Re: Effect of Pwr-Gnd plane pairing vs. non-paired planes on signal return currents -
» [SI-LIST] Re: Effect of Pwr-Gnd plane pairing vs. non-paired planes on signal return currents -
» [SI-LIST] Re: Effect of Pwr-Gnd plane pairing vs. non-paired planes on signal return currents -
» [SI-LIST] Re: Effect of Pwr-Gnd plane pairing vs. non-paired planes on signal return currents -
» [SI-LIST] Re: Effect of Pwr-Gnd plane pairing vs. non-paired planes on signal return currents -
» [SI-LIST] Re: Effect of Pwr-Gnd plane pairing vs. non-paired planes on signal return currents -
» [SI-LIST] Re: Effect of Pwr-Gnd plane pairing vs. non-paired planes on signal return currents -
» [SI-LIST] Re: HSPICE - adding jitter to ethernet serial link -
» [SI-LIST] Re: Effect of Pwr-Gnd plane pairing vs. non-paired planes on signal return currents -
» [SI-LIST] Effect of Pwr-Gnd plane pairing vs. non-paired planes on signal return currents -
» [SI-LIST] Re: DesignCon 2006 material on power distribution network design methodologies posted -
» [SI-LIST] Re: HSPICE - adding jitter to ethernet serial link -
» [SI-LIST] Re: HSPICE - adding jitter to ethernet serial link -
» [SI-LIST] Re: HSPICE - adding jitter to ethernet serial link -
» [SI-LIST] Re: DesignCon 2006 material on power distribution network design methodologies posted -
» [SI-LIST] Re: AC termination -
» [SI-LIST] Re: HSPICE - adding jitter to ethernet serial link -
» [SI-LIST] controlling test variables during troubleshooting -
» [SI-LIST] Re: HSPICE - adding jitter to ethernet serial link -
» [SI-LIST] Re: HSPICE - adding jitter to ethernet serial link -
» [SI-LIST] Re: HSPICE - adding jitter to ethernet serial link -
» [SI-LIST] Re: HSPICE - adding jitter to ethernet serial link -
» [SI-LIST] Re: HSPICE - adding jitter to ethernet serial link -
» [SI-LIST] Re: Differential Impedance of PCB Vias -
» [SI-LIST] Re: HSPICE - adding jitter to ethernet serial link -
» [SI-LIST] Re: HSPICE - adding jitter to ethernet serial link -
» [SI-LIST] Re: currnet through wire bond -
» [SI-LIST] Re: HSPICE - adding jitter to ethernet serial link -
» [SI-LIST] Re: HSPICE - adding jitter to ethernet serial link -
» [SI-LIST] Re: HSPICE - adding jitter to ethernet serial link -
» [SI-LIST] Re: HSPICE - adding jitter to ethernet serial link -
» [SI-LIST] Re: HSPICE - adding jitter to ethernet serial link -
» [SI-LIST] Re: HSPICE - adding jitter to ethernet serial link -
» [SI-LIST] Re: HSPICE - adding jitter to ethernet serial link -
» [SI-LIST] Re: HSPICE - adding jitter to ethernet serial link -
» [SI-LIST] Re: Differential Impedance of PCB Vias -
» [SI-LIST] Ethernet standards coding and data frequency -
» [SI-LIST] Re: HSPICE - adding jitter to ethernet serial link -
» [SI-LIST] Re: Differential Impedance of PCB Vias -
» [SI-LIST] Re: Differential Impedance of PCB Vias -
» [SI-LIST] Re: HSPICE - adding jitter to ethernet serial link -
» [SI-LIST] Re: HSPICE - adding jitter to ethernet serial link -
» [SI-LIST] Re: currnet through wire bond -
» [SI-LIST] Re: currnet through wire bond -
» [SI-LIST] Re: 3D tool: CST / HFSS -
» [SI-LIST] QLOGIC Ref. Designs -
» [SI-LIST] Re: Package SI vs PCB SI -
» [SI-LIST] Re: Package SI vs. PCB SI...thanks to Maxwell -
» [SI-LIST] Re: Package SI vs. PCB SI -
» [SI-LIST] Re: Package SI vs PCB SI -
» [SI-LIST] Re: Package SI vs PCB SI -
» [SI-LIST] Package SI vs PCB SI -
» [SI-LIST] Re: Analog, "low-noise", "high frequency", board-level designerneeded! -
» [SI-LIST] Re: Good book -
» [SI-LIST] Analog, "low-noise", "high frequency", board-level designer needed! -
» [SI-LIST] Signal Integrity Simplified book -
» [SI-LIST] Re: [OFF-TOPIC] Signal Integrity Simplified book -
» [SI-LIST] Re: [OFF-TOPIC] Signal Integrity Simplified book -
» [SI-LIST] Re: Good book -
» [SI-LIST] Re: [OFF-TOPIC] Signal Integrity Simplified book -
» [SI-LIST] Re: [OFF-TOPIC] Signal Integrity Simplified book -
» [SI-LIST] Re: [OFF-TOPIC] Signal Integrity Simplified book -
» [SI-LIST] Re: [OFF-TOPIC] Signal Integrity Simplified book -
» [SI-LIST] Re: [OFF-TOPIC] Signal Integrity Simplified book -
» [SI-LIST] Re: Differential Impedance of PCB Vias -
» [SI-LIST] Differential Impedance of PCB Vias -
» [SI-LIST] Fwd: EMCS-SCV Chapter Meeting, Tuesday February 14, 2006 -
» [SI-LIST] Re: Capacitor Arrays for clock AC coupling -
» [SI-LIST] Re: [OFF-TOPIC] Signal Integrity Simplified book -
» [SI-LIST] Re: Capacitor Arrays for clock AC coupling -
» [SI-LIST] Re: Capacitor Arrays for clock AC coupling -
» [SI-LIST] Re: Capacitor Arrays for clock AC coupling -
» [SI-LIST] Re: [OFF-TOPIC] Signal Integrity Simplified book -
» [SI-LIST] Capacitor Arrays for clock AC coupling -
» [SI-LIST] Re: currnet through wire bond -
» [SI-LIST] Re: [OFF-TOPIC] Signal Integrity Simplified book -
» [SI-LIST] Re: [OFF-TOPIC] Signal Integrity Simplified book -
» [SI-LIST] [OFF-TOPIC] Signal Integrity Simplified book -
» [SI-LIST] Re: AC termination -
» [SI-LIST] Microprocessor Platform Impedance. Characterization using VTT Tools -
» [SI-LIST] currnet through wire bond -
» [SI-LIST] Re: Xilinx simulation model validation -
» [SI-LIST] Xilinx simulation model validation -
» [SI-LIST] Signal Integrity Engineering position at Intel Corporation -
» [SI-LIST] AC termination -
» [SI-LIST] Re: 3D tool: CST / HFSS -
» [SI-LIST] UnSubscribe -
» [SI-LIST] Re: 3D tool: CST / HFSS -
» [SI-LIST] Re: 3D tool: CST / HFSS -
» [SI-LIST] Interesting announcement regarding IBIS 4.1 -
» [SI-LIST] Re: Skewed Silicon Parameters -
» [SI-LIST] Re: Reflections -
» [SI-LIST] Re: Reflections -
» [SI-LIST] Re: Reflections -
» [SI-LIST] Reflections -
» [SI-LIST] Re: PHY PCS -
» [SI-LIST] Re: Skewed Silicon Parameters -
» [SI-LIST] Skewed Silicon Parameters -
» [SI-LIST] 3D tool: CST / HFSS -
» [SI-LIST] Re: HSPICE - adding jitter to ethernet serial link -
» [SI-LIST] HSPICE - adding jitter to ethernet serial link -
» [SI-LIST] Re: PHY PCS -
» [SI-LIST] Re: Help me -
» [SI-LIST] Re: PHY PCS -
» [SI-LIST] Ethernet Multiplexers/Switches -
» [SI-LIST] Immunity to nearby wireless devices and EE undergrad programs -
» [SI-LIST] unsubscribe -
» [SI-LIST] unsubscribe -
» [SI-LIST] Re: Good book -
» [SI-LIST] Re: Help me -
» [SI-LIST] Re: Help me -
» [SI-LIST] Re: Help me -
» [SI-LIST] Ground/Power electrical modeling battery powered devices -
» [SI-LIST] Re: edge coupled coated microstrip differential impedance -
» [SI-LIST] Re: Good book -
» [SI-LIST] Re: Good book -
» [SI-LIST] Analog/mixed signal Contract Engineer position -
» [SI-LIST] Re: edge coupled coated microstrip differential impedance -
» [SI-LIST] Good book -
» [SI-LIST] Re: help me -
» [SI-LIST] Re: help me -
» [SI-LIST] Re: help me -
» [SI-LIST] Re: File Extension .fig -
» [SI-LIST] File Extension .fig -
» [SI-LIST] Re: help me -
» [SI-LIST] Devlopment Eng. R.F. Filter Connectors -
» [SI-LIST] Re: edge coupled coated microstrip differentialimpedance -
» [SI-LIST] Re: help me -
» [SI-LIST] Re: help me -
» [SI-LIST] Re: help me -
» [SI-LIST] Re: help me -
» [SI-LIST] Re: help me -
» [SI-LIST] Re: help me -
» [SI-LIST] help me -
» [SI-LIST] Re: edge coupled coated microstrip differential impedance -
» [SI-LIST] Session of interest to SI engineers at DesignCon 2006 -
» [SI-LIST] Re: edge coupled coated microstrip differential impedance -
» [SI-LIST] Re: Reflected Wave Switching - Silly Question. -
» [SI-LIST] Re: edge coupled coated microstrip differential impedance -
» [SI-LIST] edge coupled coated microstrip differential impedance -
» [SI-LIST] Re: Reflected Wave Switching - Silly Question. -
» [SI-LIST] Re: PHY PCS -
» [SI-LIST] Re: PHY PCS -
» [SI-LIST] Re: PHY PCS -
» [SI-LIST] Re: PHY PCS -
» [SI-LIST] PHY PCS -
» [SI-LIST] simulating mobile phone effects on circuits -
» [SI-LIST] Reflected Wave Switching - Silly Question. -
» [SI-LIST] Re: .tr0 file viewer -
» [SI-LIST] European IBIS Summit at DATe 2006 - Third Call for Paper/Call for Participation -
» [SI-LIST] Re: .tr0 file viewer -
» [SI-LIST] Re: .tr0 file viewer -
» [SI-LIST] .tr0 file viewer -
» [SI-LIST] Differential impedance signals????? -