[SI-LIST] Re: Ground Pour in Signal Layers
- From: "Haller, Robert" <rhaller@xxxxxxxxxxxxx>
- To: <leeritchey@xxxxxxxxxxxxx>
- Date: Mon, 27 Feb 2006 13:35:12 -0500
Lee,
I spoke with a few process engineers and have learned something,
and felt compelled to respond to inform (I do not intent to offend).
Copper pour or thieving on inner layers, I have been told by two
separate processing engineers can lead to "better lamination", and as
always it depends on the circuit.
One example is if you are using very thin cores (i.e. BC) and the
circuit has large areas void of copper you may get curling. The final
layer stack may yield poor lamination (delamination), have increased
stresses and possible registration issues. =20
PCB processes today have not changed that much (in fact they have
changed too little IMHO when compared to semiconductor advances), so I
would respectively disagree that the past is in fact relevant.=20
Regards,
Bob=20
-----Original Message-----
From: Lee Ritchey [mailto:leeritchey@xxxxxxxxxxxxx]=20
Sent: Thursday, February 23, 2006 5:41 PM
To: Haller, Robert; Chris Padilla (cpad); ivorlist@xxxxxxxxxxx;
Pradeep.RSA@xxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: Ground Pour in Signal Layers
Etching and plating are two very different operations. Plating depends
on
uniform current distribution. Etching is done by spraying etchant onto
the
surface and proceeds at the same rate over the entire surface. All you
gotta do is ask a process engineer at a currently operating fab shop to
see
if thieving is needed on inner layers. every time I ask, the answer is
no.
What may have been at some point in the past is not relevant. What is,
is
what todays' fabricators need and theiving on inner layers is not one of
them..
> [Original Message]
> From: Haller, Robert <rhaller@xxxxxxxxxxxxx>
> To: <leeritchey@xxxxxxxxxxxxx>; Chris Padilla (cpad) <cpad@xxxxxxxxx>;
<ivorlist@xxxxxxxxxxx>; <Pradeep.RSA@xxxxxxxxxxxx>
> Cc: <si-list@xxxxxxxxxxxxx>
> Date: 2/23/2006 11:54:20 AM
> Subject: [SI-LIST] Re: Ground Pour in Signal Layers
>
> Lee, Chris
> I worked in a board shop many years ago. My understanding of the
> original intention of adding thieving to signal layers was to promote
> consistent etching (or plating) and as a result even distribution of
> etch widths. The chemical process of etching inner layers is in
general
> more consistent if there is an even distribution of copper across the
> panel (subtractive or additive processes - etching or plating both
> benefits).=3D20
>
> There are numerous subtleties like etching/plating varies from center
to
> edge of the panel and what specific type of additive or subtractive
> processes, chemicals, electro plating, ... you are using.
> =3D20
> As folks have pointed out you must be very careful with spacing to
> critical signals and adjacent layer stripline pairs.=3D20
>
> We had some interesting arguments at the dinner table when
> "Auto-thieving" was first introduces at Digital - my brother is a
> Chemical Engineer, my mom is a Produce-ability (Manufacturing)
Engineer
> and I am an EE .....
>
> Regards,
> Bob Haller
> Enterasys Networks=3D20
>
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf of Lee Ritchey
> Sent: Thursday, February 23, 2006 12:31 PM
> To: Chris Padilla (cpad); ivorlist@xxxxxxxxxxx;
Pradeep.RSA@xxxxxxxxxxxx
> Cc: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Ground Pour in Signal Layers
>
> Chris,
>
> Of the three reasons listed below, only number 2 is of value. Shield
> islands don't really do that. They may induce cross talk.
Fabricators
> don't need fill in signal layers to prevent warpage. I'm not sure
where
> that one got started. Also, doesn't help control impedance, but
rather,
> can make it drop if the fill is too close.
>
> Don't mean to offend anyone with these answers, but the record needs
to
> be
> set straight.
>
>
> > [Original Message]
> > From: Chris Padilla (cpad) <cpad@xxxxxxxxx>
> > To: <ivorlist@xxxxxxxxxxx>; <Pradeep.RSA@xxxxxxxxxxxx>
> > Cc: <si-list@xxxxxxxxxxxxx>
> > Date: 2/23/2006 8:53:40 AM
> > Subject: [SI-LIST] Re: Ground Pour in Signal Layers
> >
> > "Ground" pour can serve several purposes:
> >
> > (1) Create shielded islands
> > (2) Create some extra interplane capacitance (not sure how useful it
> is
> > for charge storage as it is most likely located electrically far
from
> > the chip needing the current)
> > (3) Balance out a layer to avoid warpage issues and to ensure better
> > trace dimension (impedance) control
> >
> > I think (3) is the big one: Fab shops often request the ability to
> add
> > "thieving" in areas of sparse metal. Some folks just go ahead and
add
> > the metal pour and often sink several "ground" vias through it to
> > connect it up to something. I forget the details why, but the fab
> shops
> > have better control of trace width if they don't have to etch away a
> lot
> > of metal.
> >
> > As in all cases, such items can cause problems if not carefully
> handled
> > and thought through.
> >
> > Chris Padilla
> > Cisco Systems
> > San Jose, CA
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