[SI-LIST] Re: DesignCon Papers
- From: "Peterson, James F (FL51)" <james.f.peterson@xxxxxxxxxxxxx>
- To: 'silist' <si-list@xxxxxxxxxxxxx>
- Date: Tue, 8 Feb 2005 05:52:31 -0700
Reasonable questions Bob. We should always carefully evaluate the worth of
SI practices. We should always try to verify by measurement some of what we
simulate. We should always try to understand why they don't agree. If we do
this, then we gain more confidence in our simulations and they become more
accurate.
Years ago when we didn't have to worry about this as much, our FPGAs and
large components had less current and higher voltages. My current design's
FPGA has a core voltage of 1.5V and dynamic current of 5A. At +/-5% I have
to stay within 75mV of that voltage and deliver 5A (that's 15mOhms). Now if
i don't simulate to verify my circuitry, and I just throw some caps at it,
it might still work in the lab - after all there is some margin in that +/-
5%, but what happens to my company's profits if it has to recall 1% of 10's
of thousands of shipped products because of intermittent failures. (One of
my professors at school use to tell me "doctors can kill people one at a
time, but engineers can kill 100s at a time" - well, engineers also have the
power to kill companies.)
Also, it's been my impression that the more I simulate the less conservative
I become.
Finally, I don't believe PI simulation is expensive (an eval copy of SPICE
might do it).
Jim Peterson
Honeywell
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Robert Sefton
Sent: Tuesday, February 08, 2005 12:40 AM
To: 'silist'
Subject: [SI-LIST] Re: DesignCon Papers
Dear list, especially the power integrity experts and pioneers at Sun,
Teraspeed, et al -
I've been a list member for more than five years now - rarely contributing,
but religiously monitoring the dialogue. In the 15+ years I've been in this
business I've been responsible for or at least been involved in dozens of
large PCB designs. Over all of those designs I've seen maybe 4-5 signal
integrity problems (where operation was affected), but I have never, ever
seen a power integrity problem. Virtually all of these designs have included
at least one FPGA, a processor, and SRAM and/or SDRAM. And several have
included FPGAs plus ICs dissipating 20+ watts with SPI-4.2, SerDes, DDR, and
other high speed interfaces.
I'm a consultant, and I primarily work with small start-up companies that
have no budget and no inclination for SI tools. (They'll spend many $100Ks
or even $1Ms on IC tools, but won't spend a dime on PCB tools other than
schematic entry and layout.) Probably half of the boards I've been involved
with are prototype builds where schedule is paramount. With these I can
rarely exert enough control to get the layout exactly like I want, and often
the boards go out with serious reservations on my part. I always try to
observe the prevailing guidelines expressed here and elsewhere, but I've
seen boards go out with barely any copper left in the "planes" beneath large
power-hungry BGA parts due to poor via placement and large anti-pads. I
recently saw a board come back where a large Virtex-II FPGA would not
configure. It was traced down to the fact that the core power islands under
the BGA were were so sliced up that they were not connected to the core
power VRM. The swiss cheese core power "plane" was re-connected to the +1.5V
supply with a 4" blue wire through one via on the bottom of the board. Guess
what - it worked like a champ.
I'm not trying to be an ass here (I'll leave that to Chris C. :`)), but I'm
really beginning to question the need for some or even most of the
theoretical PI analyses espoused here. I can't believe that luck has made
all of my boards work over the years, despite not having access to SI or PI
tools of any kind. What I really think is going on is that there are very
few designs that need the ultra-low-mOhm, highly-simulated, and
highly-engineered power distribution methodologies that have been discussed
here recently. I'll be damned if I can make a board NOT work due to how
power is distributed.
In the PI discussions on the SI-list I almost never hear power/current
levels discussed. I'm sure that Sun cranks out boards with processor ICs or
modules that draw 10s of Amps of core power, where detailed analysis of the
PDS is critical. But what about us mortals who design run-of-the-mill FPGA +
PowerPC + MAC, etc., type of boards? As I said, despite some brutally bad
layouts, I have NEVER had a problem related to power distribution.
I have two requests to the list:
1. When espousing SI and/or PI practices, please be as specific as possible
about when these practices are warranted, and more importantly, when they
are not.
2. I would LOVE to hear more detailed reports from the trenches (i.e. war
stories) about SI and PI problems that were actually seen on real boards
(not in simulation), and how they were fixed. This is something that is
almost NEVER discussed amongst the regulars here.
I have a strong sense that non-experts (like me) who monitor this list are
buying into methods that may not apply to their designs and are therefore
over-engineering (one of my least favorite things - I prefer to
under-engineer and get away with it).
All comments are welcome.
Best regards,
Bob Sefton
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