Posts for si-list, 02-2005

Browse: Last Month: 01-2005 Main Archive Page Next Month: 03-2005

» [SI-LIST] Re: DDR simulation -
» [SI-LIST] Re: creating an IBIS model... -
» [SI-LIST] Re: creating an IBIS model... -
» [SI-LIST] Re: Electrically conductive Epoxy -
» [SI-LIST] Re: DDR simulation -
» [SI-LIST] creating an IBIS model... -
» [SI-LIST] Re: Driver Output Impedance am I doing this correctly? -
» [SI-LIST] Re: Driver Output Impedance am I doing this correctly? -
» [SI-LIST] Re: Driver Output Impedance am I doing this correctly? -
» [SI-LIST] Re: Driver Output Impedance am I doing this correctly? -
» [SI-LIST] Re: Driver Output Impedance am I doing this correctly? -
» [SI-LIST] Re: Driver Output Impedance am I doing this correctly? -
» [SI-LIST] Hi this is Manish -
» [SI-LIST] Re: DDR simulation -
» [SI-LIST] Re: DDR simulation -
» [SI-LIST] DDR simulation -
» [SI-LIST] IBIS and SI talks at Mentor' User2User Conference -
» [SI-LIST] S2IBIS3 V1.0 released. -
» [SI-LIST] Re: Converting SPICE rlgc files into ADS -
» [SI-LIST] Re: Necessity of Ground signal for RS485 transmission at 500 ft cable length -
» [SI-LIST] Re: R: LVDS Simulation? -
» [SI-LIST] Re: Necessity of Ground signal for RS485 transmission at 500 ft cable length -
» [SI-LIST] Re: Necessity of Ground signal for RS485 transmission at 500 ft cable length -
» [SI-LIST] Re: Necessity of Ground signal for RS485 transmission at 500 ft cable length -
» [SI-LIST] Re: si-list Digest V5 #86 -
» [SI-LIST] Re: Converting SPICE rlgc files into ADS -
» [SI-LIST] Re: Good physical description of skin effect -
» [SI-LIST] Re: Converting SPICE rlgc files into ADS -
» [SI-LIST] Re: Dielectric nature of Substrate -
» [SI-LIST] Re: Dielectric nature of Substrate -
» [SI-LIST] Re: Dielectric nature of Substrate -
» [SI-LIST] Re: using spice to calculate driver output impedance -
» [SI-LIST] Re: Dielectric nature of Substrate -
» [SI-LIST] Re: Dielectric nature of Substrate -
» [SI-LIST] Re: Dielectric nature of Substrate -
» [SI-LIST] Good physical description of skin effect -
» [SI-LIST] Re: using spice to calculate driver output impedance -
» [SI-LIST] Re: Dielectric nature of Substrate -
» [SI-LIST] Dielectric nature of Substrate -
» [SI-LIST] Re: Necessity of Ground signal for RS485 transmission at 500 ft cable length -
» [SI-LIST] Re: Necessity of Ground signal for RS485 transmission at 500 ft cable length -
» [SI-LIST] Re: Necessity of Ground signal for RS485 transmission at 500 ft cable length -
» [SI-LIST] Necessity of Ground signal for RS485 transmission at 500 ft cable length -
» [SI-LIST] Re: R: LVDS Simulation? -
» [SI-LIST] R: LVDS Simulation? -
» [SI-LIST] LVDS Simulation? -
» [SI-LIST] Re: Looking for information on AMS Modeling -
» [SI-LIST] Re: Looking for information on AMS Modeling -
» [SI-LIST] Re: How to get the load capacitance of input buffer by means of HSPICE model -
» [SI-LIST] Re: How to get the load capacitance of input buffer by means of HSPICE model -
» [SI-LIST] Re: How to get the load capacitance of input buffer by means of HSPICE model -
» [SI-LIST] How to get the load capacitance of input buffer by means of HSPICE model -
» [SI-LIST] Re: using spice to calculate driver output impedance -
» [SI-LIST] Re: using spice to calculate driver output impedance -
» [SI-LIST] Driver Output Impedance am I doing this correctly? -
» [SI-LIST] Re: Hspice vs. Eldo w hspice compatibility mode -
» [SI-LIST] Re: Skin Effect, Au, and Cu -
» [SI-LIST] Re: Skin Effect, Au, and Cu -
» [SI-LIST] Re: Skin Effect, Au, and Cu -
» [SI-LIST] Re: Skin Effect, Au, and Cu -
» [SI-LIST] Re: Skin Effect, Au, and Cu -
» [SI-LIST] Electrically conductive Epoxy -
» [SI-LIST] Skin Effect, Au, and Cu -
» [SI-LIST] Re: using spice to calculate driver output impedance -
» [SI-LIST] RIMM connector for RDRAM -
» [SI-LIST] Re: using spice to calculate driver output impedance -
» [SI-LIST] ICM Draft Ver. 1.1 documents now available for review -
» [SI-LIST] using spice to calculate driver output impedance -
» [SI-LIST] Re: Intel Motherboard with DDR2 -
» [SI-LIST] Re: Intel Motherboard with DDR2 -
» [SI-LIST] Re: si-list Digest V5 #82 -
» [SI-LIST] Re: Current Seminars on High-Speed Issues -
» [SI-LIST] Re: Intel Motherboard with DDR2 -
» [SI-LIST] Re: PCB stackup -
» [SI-LIST] Re: si-list Digest V5 #82 -
» [SI-LIST] Re: si-list Digest V5 #82 -
» [SI-LIST] DDR2 DIMM Question -
» [SI-LIST] DDR2 DIMM question -
» [SI-LIST] Re: Skin Effect, Au, and Cu -
» [SI-LIST] Antwort: Re: Skin Effect, Au, and Cu -
» [SI-LIST] PCB stackup -
» [SI-LIST] DDR2 DIMM question -
» [SI-LIST] Re: si-list Digest V5 #82 -
» [SI-LIST] DDR2 DIMM question -
» [SI-LIST] Re: si-list Digest V5 #82 -
» [SI-LIST] Re: Skin Effect, Au, and Cu -
» [SI-LIST] Re: si-list Digest V5 #82 -
» [SI-LIST] Re: Skin Effect, Au, and Cu -
» [SI-LIST] Re: Skin Effect, Au, and Cu -
» [SI-LIST] Re: Skin Effect, Au, and Cu -
» [SI-LIST] Current Seminars on High-Speed Issues -
» [SI-LIST] Re: support -
» [SI-LIST] Re: Skin Effect, Au, and Cu -
» [SI-LIST] Re: Intel Motherboard with DDR2 -
» [SI-LIST] Re: Skin Effect, Au, and Cu-->More details... -
» [SI-LIST] Converting SPICE rlgc files into ADS -
» [SI-LIST] Re: Skin Effect, Au, and Cu -
» [SI-LIST] Re: Skin Effect, Au, and Cu -
» [SI-LIST] Re: Skin Effect, Au, and Cu -
» [SI-LIST] Skin Effect, Au, and Cu -
» [SI-LIST] Re: support -
» [SI-LIST] Re: support -
» [SI-LIST] Re: Intel Motherboard with DDR2 -
» [SI-LIST] Re: Intel Motherboard with DDR2 -
» [SI-LIST] Re: Intel Motherboard with DDR2 -
» [SI-LIST] Re: Intel Motherboard with DDR2 -
» [SI-LIST] Re: Single ended clock from differential clock source -
» [SI-LIST] support -
» [SI-LIST] Re: Intel Motherboard with DDR2-To Scott -
» [SI-LIST] Re: Intel Motherboard with DDR2 -
» [SI-LIST] Re: Intel Motherboard with DDR2 -
» [SI-LIST] Re: Intel Motherboard with DDR2 -
» [SI-LIST] Re: Intel Motherboard with DDR2 -
» [SI-LIST] European IBIS Summit @ DATe 2005 - Third Call for Participation -
» [SI-LIST] Re: Intel Motherboard with DDR2 -
» [SI-LIST] Re: Intel Motherboard with DDR2 -
» [SI-LIST] Re: Intel Motherboard with DDR2 -
» [SI-LIST] Re: Intel Motherboard with DDR2 -
» [SI-LIST] Re: single end and bused trace question -
» [SI-LIST] Re: Intel Motherboard with DDR2 -
» [SI-LIST] Re: Intel Motherboard with DDR2 -
» [SI-LIST] Re: single end and bused trace question -
» [SI-LIST] Re: Intel Motherboard with DDR2 -
» [SI-LIST] Re: Intel Motherboard with DDR2 -
» [SI-LIST] Re: single end and bused trace question -
» [SI-LIST] Re: Intel Motherboard with DDR2 -
» [SI-LIST] Re: Stackups with Microvias -
» [SI-LIST] Re: Intel Motherboard with DDR2 -
» [SI-LIST] Re: Intel Motherboard with DDR2 -
» [SI-LIST] Re: single end and bused trace question -
» [SI-LIST] Single ended clock from differential clock source -
» [SI-LIST] Re: Stackups with Microvias -
» [SI-LIST] Re: Stackups with Microvias -
» [SI-LIST] Re: Intel Motherboard with DDR2 -
» [SI-LIST] Re: Intel Motherboard with DDR2 -
» [SI-LIST] Re: Intel Motherboard with DDR2 -
» [SI-LIST] Re: Intel Motherboard with DDR2 -
» [SI-LIST] Re: Intel Motherboard with DDR2 -
» [SI-LIST] Re: single end and bused trace question -
» [SI-LIST] Re: Intel Motherboard with DDR2 -
» [SI-LIST] Intel Motherboard with DDR2 -
» [SI-LIST] Re: single end and bused trace question -
» [SI-LIST] Re: single end and bused trace question -
» [SI-LIST] Re: Stackups with Microvias -
» [SI-LIST] Basic DDRII question -
» [SI-LIST] Stackups with Microvias -
» [SI-LIST] single end and bused trace question -
» [SI-LIST] Re: FLOATING NODE IN PSPICE -
» [SI-LIST] Re: FLOATING NODE IN PSPICE -
» [SI-LIST] Re: FLOATING NODE IN PSPICE -
» [SI-LIST] Are Lead Free fully backwards compatible? -
» [SI-LIST] SPICE Flattener, Plane Breaks, Benchmarking -
» [SI-LIST] Re: FLOATING NODE IN PSPICE -
» [SI-LIST] FLOATING NODE IN PSPICE -
» [SI-LIST] posted: DesignCon TecForum TF7 on Inductance of Bypass Capacitors -
» [SI-LIST] New College Graduate SI Opportunity -
» [SI-LIST] Re: Hspice vs. Eldo w hspice compatibility mode -
» [SI-LIST] designof a fault tolerant clock -
» [SI-LIST] Re: 50 Gbps interconnect paper (resubmit) -
» [SI-LIST] 50 Gbps interconnect paper -
» [SI-LIST] RMCEMC Career Ops Update - URL included -
» [SI-LIST] Re: Switch On & Switch Off Clicks due to Amplifier noise -
» [SI-LIST] Re: Switch On & Switch Off Clicks due to Amplifier noise -
» [SI-LIST] Re: S-parameter passivity -
» [SI-LIST] Re: checking consistency between behavioural and .lib view od HARDIPs -
» [SI-LIST] Re: Switch On & Switch Off Clicks due to Amplifier noise -
» [SI-LIST] Re: Switch On & Switch Off Clicks due to Amplifier noise -
» [SI-LIST] FW: Re: Switch On & Switch Off Clicks due to Amplifier noise -
» [SI-LIST] checking consistency between behavioural and .lib view od HARDIPs -
» [SI-LIST] Re: Switch On & Switch Off Clicks due to Amplifier noise -
» [SI-LIST] Switch On & Switch Off Clicks due to Amplifier noise -
» [SI-LIST] Re: S-parameter passivity -
» [SI-LIST] RMCEMC Career Ops page Update -
» [SI-LIST] Re: DesignCon Papers -
» [SI-LIST] Re: DesignCon Papers -
» [SI-LIST] Re: DesignCon Papers -
» [SI-LIST] Hspice vs. Eldo w hspice compatibility mode -
» [SI-LIST] Re: SI analysis input parameters -
» [SI-LIST] Re: S-parameter passivity -
» [SI-LIST] Re: S-parameter passivity -
» [SI-LIST] Re: SI analysis input parameters -
» [SI-LIST] Re: SI analysis input parameters -
» [SI-LIST] Re: S-parameter passivity -
» [SI-LIST] Re: SI analysis input parameters -
» [SI-LIST] S-parameter passivity -
» [SI-LIST] SI analysis input parameters -
» [SI-LIST] Re: SI-related Cartoon -
» [SI-LIST] Re: Formula page and guides on SI -
» [SI-LIST] Re: Formula page and guides on SI -
» [SI-LIST] Re: Formula page and guides on SI -
» [SI-LIST] Re: Fan-out in TTL and CMOS -
» [SI-LIST] Re: Formula page and guides on SI -
» [SI-LIST] Re: Fan-out in TTL and CMOS -
» [SI-LIST] Re: Formula page and guides on SI -
» [SI-LIST] Presentations from IBIS Summit at DesignCon 2005 now on-line! -
» [SI-LIST] Re: Formula page and guides on SI -
» [SI-LIST] Re: Formula page and guides on SI -
» [SI-LIST] Formula page and guides on SI -
» [SI-LIST] Re: SPICE flattening -
» [SI-LIST] Re: SPICE flattening -
» [SI-LIST] Re: SPICE flattening -
» [SI-LIST] SPICE flattening -
» [SI-LIST] Re: SI-related Cartoon -
» [SI-LIST] Re: SI-related Cartoon -
» [SI-LIST] Re: DesignCon Papers -
» [SI-LIST] Re: Simple H-Spice Question -
» [SI-LIST] Re: SI-related Cartoon -
» [SI-LIST] Re: routing of Ethernet pairs -
» [SI-LIST] inductance of coupled shielded odd mode stripline -
» [SI-LIST] Re: routing of Ethernet pairs -
» [SI-LIST] Re: Transmission Line question -
» [SI-LIST] Re: about golden standard -
» [SI-LIST] routing of Ethernet pairs -
» [SI-LIST] Transmission Line question -
» [SI-LIST] Re: How to Measure Inductance of Pads, Vias, and Planes: Can ESL be defined as a property of the capacitor? -
» [SI-LIST] Re: Simple H-Spice Question -
» [SI-LIST] Re: S-Parameter manipulations -
» [SI-LIST] Re: Simple H-Spice Question -
» [SI-LIST] Re: DesignCon Papers -
» [SI-LIST] Re: DesignCon Papers -
» [SI-LIST] Re: DesignCon Papers -
» [SI-LIST] Re: DesignCon Papers -
» [SI-LIST] Re: Near End TDR Measurement/Simulation -
» [SI-LIST] Re: DesignCon Papers -
» [SI-LIST] Re: DesignCon Papers -
» [SI-LIST] Re: about golden standard -
» [SI-LIST] Re: Simple H-Spice Question -
» [SI-LIST] Re: S-Parameter manipulations -
» [SI-LIST] Re: DesignCon Papers -
» [SI-LIST] Re: S parameter manipulations -
» [SI-LIST] Re: about golden standard -
» [SI-LIST] Re: Cascading T-Lines -
» [SI-LIST] Re: S parameter manipulations -
» [SI-LIST] Re: DesignCon Papers -
» [SI-LIST] Re: How to Measure Inductance of Pads, Vias, and Planes: Can ESL be defined as a property of the capacitor? -
» [SI-LIST] Re: DesignCon Papers -
» [SI-LIST] Re: S-Parameter manipulations -
» [SI-LIST] Simple H-Spice Question -
» [SI-LIST] S-Parameter manipulations -
» [SI-LIST] Re: Input Clock phase noise and TX eye closurein SERDES -
» [SI-LIST] Near End TDR Measurement/Simulation -
» [SI-LIST] Designcon Paper and Presentation -
» [SI-LIST] Re: DesignCon Papers -
» [SI-LIST] about golden standard -
» [SI-LIST] Re: inductance of differential stripline -
» [SI-LIST] Re: inductance of differential stripline -
» [SI-LIST] Re: inductance of differential stripline -
» [SI-LIST] Re: inductance of differential stripline -
» [SI-LIST] Re: DesignCon Papers -
» [SI-LIST] Re: Fan-out in TTL and CMOS -
» [SI-LIST] Re: inductance of differential stripline -
» [SI-LIST] Re: DesignCon Papers -
» [SI-LIST] Re: How to Measure Inductance of Pads, Vias, and Planes -
» [SI-LIST] Feb-2005 IEEE-EMCS Santa Clara Valley chapter meeting -
» [SI-LIST] How to Measure Inductance of Pads, Vias, and Planes -
» [SI-LIST] Re: Input Clock phase noise and TX eye closurein SERDES -
» [SI-LIST] Re: Post Designcon thread -
» [SI-LIST] DesignCon Papers -
» [SI-LIST] Re: Post Designcon thread -
» [SI-LIST] Re: Post Designcon thread -
» [SI-LIST] Re: Is there other SI tool that similar to ICX? -
» [SI-LIST] Re: inductance of differential stripline -
» [SI-LIST] inductance of differential stripline -
» [SI-LIST] Re: Reference plane resonance -
» [SI-LIST] Re: Reference plane resonance -
» [SI-LIST] Reference plane resonance -
» [SI-LIST] Re: Query CMOS FPGA interface -
» [SI-LIST] Re: Query CMOS FPGA interface -
» [SI-LIST] Re: DDR-1 termination (short point-to-point) -
» [SI-LIST] more data on plane breaks -
» [SI-LIST] Re: Is there other SI tool that similar to ICX? -
» [SI-LIST] Re: DDR-1 termination (short point-to-point) -
» [SI-LIST] Re: DDR-1 termination (short point-to-point) -
» [SI-LIST] Re: Post Designcon thread -
» [SI-LIST] Re: Query CMOS FPGA interface -
» [SI-LIST] Re: Query CMOS FPGA interface -
» [SI-LIST] Re: Query CMOS FPGA interface -
» [SI-LIST] Re: Is there other SI tool that similar to ICX? -
» [SI-LIST] Re: Post Designcon thread -
» [SI-LIST] Query CMOS FPGA interface -
» [SI-LIST] Re: Fan-out in TTL and CMOS -
» [SI-LIST] Re: Fan-out in TTL and CMOS -
» [SI-LIST] Re: Fan-out in TTL and CMOS--> There are some interesting high speed parts available in ECL -
» [SI-LIST] Re: Fan-out in TTL and CMOS -
» [SI-LIST] Re: Fan-out in TTL and CMOS -
» [SI-LIST] Re: Fan-out in TTL and CMOS -
» [SI-LIST] Re: Fan-out in TTL and CMOS -
» [SI-LIST] Re: Fan-out in TTL and CMOS -
» [SI-LIST] Re: Post Designcon thread -
» [SI-LIST] Re: Fan-out in TTL and CMOS -
» [SI-LIST] Re: DDR-1 termination (short point-to-point) -
» [SI-LIST] Re: Fan-out in TTL and CMOS -
» [SI-LIST] Re: Post Designcon thread -
» [SI-LIST] Re: Post Designcon thread -
» [SI-LIST] Re: DDR-1 termination (short point-to-point) -
» [SI-LIST] Re: DDR-1 termination (short point-to-point) -
» [SI-LIST] Re: DDR-1 termination (short point-to-point) -
» [SI-LIST] Is there other SI tool that similar to ICX? -
» [SI-LIST] Re: Post Designcon thread -
» [SI-LIST] Re: DDR-1 termination (short point-to-point) -
» [SI-LIST] Re: Spice -
» [SI-LIST] Re: Fan-out in TTL and CMOS -
» [SI-LIST] Re: DDR-1 termination (short point-to-point) -
» [SI-LIST] Re: DDR-1 termination (short point-to-point) -
» [SI-LIST] Re: DDR-1 termination (short point-to-point) -
» [SI-LIST] Re: DDR-1 termination (short point-to-point) -
» [SI-LIST] Re: DDR-1 termination (short point-to-point) -
» [SI-LIST] DDR-1 termination (short point-to-point) -
» [SI-LIST] Re: Post Designcon thread -
» [SI-LIST] Fan-out in TTL and CMOS -
» [SI-LIST] Post Designcon thread -
» [SI-LIST] Re: Spice -
» [SI-LIST] Re: Spice -
» [SI-LIST] Re: Spice -
» [SI-LIST] Re: Spice -
» [SI-LIST] Spice -
» [SI-LIST] Re: Allegro PCB-SI "Model Integrity" for IBIS Development -
» [SI-LIST] Re: Input Clock phase noise and TX eye closurein SERDES -
» [SI-LIST] Allegro PCB-SI "Model Integrity" for IBIS Development -
» [SI-LIST] Re: Input Clock phase noise and TX eye closurein SERDES -
» [SI-LIST] Re: - Difference between High Current Low Voltage and Low Current High Voltage circuits -
» [SI-LIST] Re: PCB high Speed Design books -
» [SI-LIST] RMCEMC January presentation download available -
» [SI-LIST] Re: Coupled & Lossy Line Model Validation Structure -
» [SI-LIST] Re: - Difference between High Current Low Voltage and Low Current High Voltage circuits -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] Re: Input Clock phase noise and TX eye closurein SERDES -
» [SI-LIST] Deadline Extension SPI 2005 -
» [SI-LIST] PCB high Speed Design books -
» [SI-LIST] Re: - Difference between High Current Low Voltage and Low Current High Voltage circuits -
» [SI-LIST] a simple question -
» [SI-LIST] Re: Input Clock phase noise and TX eye closurein SERDES -
» [SI-LIST] - Difference between High Current Low Voltage and Low Current High Voltage circuits -