[SI-LIST] Re: DesignCon Papers
- From: steve weir <weirsi@xxxxxxxxxx>
- To: chris_landrum@xxxxxxxxxx, "silist" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 11 Feb 2005 11:57:06 -0800
Chris, yes the papers are available on the Teraspeed Consulting Group
website: www.teraspeed.com.
Steve.
At 02:53 PM 2/11/2005 -0500, Landrum, Chris wrote:
>I am particularly interested in the topic of PDS design. Are the
>designcon papers published/posted anywhere?
>
>-Chris
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>On Behalf Of Steve Weir
>Sent: Tuesday, February 08, 2005 7:17 PM
>To: pzilaro@xxxxxxxxxxxx; paul.taddonio@xxxxxxxxxxxxxx;
>Chris.Cheng@xxxxxxxxxxxx; 'silist'
>Subject: [SI-LIST] Re: DesignCon Papers
>
>Patrick, I for one value Chris' contributions greatly, even if diplomacy
>
>was not his minor in college. Chris has proven that he graciously rolls
>
>with the punches as his good humor at the joke Bill Anthony and I played
>on=20
>him at DesignCon well demonstrated.
>
>Steve
>
>
>At 12:25 PM 2/8/2005 -0800, Patrick Zilaro wrote:
> >Guys,
> >
> >Chris Cheng purposely acts like this to gain notoriety for the purpose
>=3D
> >of
> >promoting his consulting services.
> >
> >Please ignore him. The more you publicly "take offense, etc.", the
>more =3D
> >he
> >is getting exactly what he wants.
> >
> >Regards,
> >
> >Patrick
> >
> >-----Original Message-----
> >From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx] =3D
> >On
> >Behalf Of Paul Taddonio
> >Sent: Tuesday, February 08, 2005 12:13 PM
> >To: Chris.Cheng@xxxxxxxxxxxx; 'silist'
> >Subject: [SI-LIST] Re: DesignCon Papers
> >
> >I object to the tone and content of this posting.
> >
> >Paul Taddonio
> >
> >----- Original Message -----=3D20
> >From: "Chris Cheng" <Chris.Cheng@xxxxxxxxxxxx>
> >To: "'silist'" <si-list@xxxxxxxxxxxxx>
> >Sent: Tuesday, February 08, 2005 2:25 PM
> >Subject: [SI-LIST] Re: DesignCon Papers
> >
> >
> > > Would you care to take the Chris Cheng challenge ?
> > >
> > > If you don't believe in PI problem. Take out all the PLLVDD filters
> >(forget
> > > about those crazy output VDD filter, which is questionable) on your
> >favorite
> > > FPGA or SerDes. Let's see how many of them fail mysteriously in the
>=3D
> >field
> >or
> > > just fall off on its face on the tester. And how long you can keep =
>=3D
> >your
> >job
> > > as a consultant. I have many of the hotshot PLL designers, system
> >designers
> > > challenging me on this. If you think I am an ass in Si-list, you =3D
> >should
> >ask
> > > those people what kind of ass I am when I start taunting them when =
>=3D
> >they
> >come
> > > back to apologize. Ask Ray and Larry's old boss for example.
> > >
> > > But seriously, ask youself this question, in your 15+ year of =3D
> >experience,
> > > how many times you have to design a 100W+ and >1GHz core chip and =
>=3D
> >package?
> > > Of those chips, how many of them has to have these superwide (288
>bit
> >width
> > > per bus) FSB on top of $ BSB with 18+ layer boards ? Like I said =3D
> >before,
> >if
> > > you are not ready to run with the big boys, stay with the crowd. The
>=3D
> >sad
> > > thing is, I can count with one hand how many of those companies can
>=3D
> >still
> > > afford to it and my thinking is it will be even less in a few years.
> > >
> > > -----Original Message-----
> > > From: Robert Sefton [mailto:rsefton@xxxxxxxxxxxxx]
> > > Sent: Monday, February 07, 2005 9:40 PM
> > > To: 'silist'
> > > Subject: [SI-LIST] Re: DesignCon Papers
> > >
> > >
> > > Dear list, especially the power integrity experts and pioneers at
>Sun,
> > > Teraspeed, et al -
> > >
> > > I've been a list member for more than five years now - rarely
> >contributing,
> > > but religiously monitoring the dialogue. In the 15+ years I've been
>in
> >this
> > > business I've been responsible for or at least been involved in
>dozens =3D
> >of
> > > large PCB designs. Over all of those designs I've seen maybe 4-5 =3D
> >signal
> > > integrity problems (where operation was affected), but I have never,
>=3D
> >ever
> > > seen a power integrity problem. Virtually all of these designs have
> >included
> > > at least one FPGA, a processor, and SRAM and/or SDRAM. And several =
>=3D
> >have
> > > included FPGAs plus ICs dissipating 20+ watts with SPI-4.2, SerDes,
>=3D
> >DDR,
> >and
> > > other high speed interfaces.
> > >
> > > I'm a consultant, and I primarily work with small start-up companies
>=3D
> >that
> > > have no budget and no inclination for SI tools. (They'll spend many
>=3D
> >$100Ks
> > > or even $1Ms on IC tools, but won't spend a dime on PCB tools other
>=3D
> >than
> > > schematic entry and layout.) Probably half of the boards I've been
> >involved
> > > with are prototype builds where schedule is paramount. With these I
>=3D
> >can
> > > rarely exert enough control to get the layout exactly like I want,
>and
> >often
> > > the boards go out with serious reservations on my part. I always try
>=3D
> >to
> > > observe the prevailing guidelines expressed here and elsewhere, but
>=3D
> >I've
> > > seen boards go out with barely any copper left in the "planes"
>beneath
> >large
> > > power-hungry BGA parts due to poor via placement and large
>anti-pads. =3D
> >I
> > > recently saw a board come back where a large Virtex-II FPGA would
>not
> > > configure. It was traced down to the fact that the core power
>islands
> >under
> > > the BGA were were so sliced up that they were not connected to the =
>=3D
> >core
> > > power VRM. The swiss cheese core power "plane" was re-connected to
>the
> >+1.5V
> > > supply with a 4" blue wire through one via on the bottom of the
>board.
> >Guess
> > > what - it worked like a champ.
> > >
> > > I'm not trying to be an ass here (I'll leave that to Chris C. :`)),
>=3D
> >but
> >I'm
> > > really beginning to question the need for some or even most of the
> > > theoretical PI analyses espoused here. I can't believe that luck has
>=3D
> >made
> > > all of my boards work over the years, despite not having access to
>SI =3D
> >or
> >PI
> > > tools of any kind. What I really think is going on is that there are
>=3D
> >very
> > > few designs that need the ultra-low-mOhm, highly-simulated, and
> > > highly-engineered power distribution methodologies that have been
> >discussed
> > > here recently. I'll be damned if I can make a board NOT work due to
>=3D
> >how
> > > power is distributed.
> > >
> > > In the PI discussions on the SI-list I almost never hear
>power/current
> > > levels discussed. I'm sure that Sun cranks out boards with processor
>=3D
> >ICs
> >or
> > > modules that draw 10s of Amps of core power, where detailed analysis
>=3D
> >of
> >the
> > > PDS is critical. But what about us mortals who design
>run-of-the-mill =3D
> >FPGA
> >+
> > > PowerPC + MAC, etc., type of boards? As I said, despite some
>brutally =3D
> >bad
> > > layouts, I have NEVER had a problem related to power distribution.
> > >
> > > I have two requests to the list:
> > >
> > > 1. When espousing SI and/or PI practices, please be as specific as
> >possible
> > > about when these practices are warranted, and more importantly, when
>=3D
> >they
> > > are not.
> > >
> > > 2. I would LOVE to hear more detailed reports from the trenches
>(i.e. =3D
> >war
> > > stories) about SI and PI problems that were actually seen on real =
>=3D
> >boards
> > > (not in simulation), and how they were fixed. This is something that
>=3D
> >is
> > > almost NEVER discussed amongst the regulars here.
> > >
> > > I have a strong sense that non-experts (like me) who monitor this
>list =3D
> >are
> > > buying into methods that may not apply to their designs and are =3D
> >therefore
> > > over-engineering (one of my least favorite things - I prefer to
> > > under-engineer and get away with it).
> > >
> > > All comments are welcome.
> > >
> > > Best regards,
> > > Bob Sefton
> > >
> > >
> > >
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