[SI-LIST] Re: Buffer delay

Hi Yan,
   IBIS models before v4.0 do not contain any internal delay modeling. I
think it is quite normal to see an offset between IBIS simulation
results and SPICE simulation results if you line up internal digital
excitation waveforms.
   I am not sure if the latest IBIS standard adds any new feature
related to internal delay.
  =20

Disclaimer:
The content of this message is my personal opinion only and although I
am an employee of Brocade Communications Systems, the statements I make
here in no way represent Brocade's position on the issue, nor am I
authorized to speak on behalf of Brocade on this matter.

Thanks=20
Tony

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of yan hang
Sent: Sunday, November 19, 2006 8:32 PM
To: si-list@xxxxxxxxxxxxx
Cc: liuweidong@xxxxxxxxxx
Subject: [SI-LIST] Re: Buffer delay

 Hello Lynne & Michael ,

 In the "IBIS QUALITY SPECIFICATION ",  it defined that the IQ3=3D20
 level--the model data for timing analysis has been checked. If there is
=3D
a
time of offset between
the two waveforms(IBIS &HSPICE),shoule we say the model can not pass the
IQ3?
When we use hspice model to create ibis model ,do we must check the =3D
offset
and correct it?

Best Regards,

Yan Hang
Huawei Technology
Shanghai Research Institute
Interconnection Dept.,R&D
Tel =3DA3=3DAB862168644808=3DA3=3DAD24043

-----=3DD3=3DCA=3DBC=3DFE=3DD4=3DAD=3DBC=3DFE-----
=3DB7=3DA2=3DBC=3DFE=3DC8=3DCB: Lynne D. Green =
[mailto:lgreen22@xxxxxxxxxxxxxx]=3D20
=3DB7=3DA2=3DCB=3DCD=3DCA=3DB1=3DBC=3DE4: =
2006=3DC4=3DEA11=3DD4=3DC218=3DC8=3DD5 3:36
=3DCA=3DD5=3DBC=3DFE=3DC8=3DCB: forsilist@xxxxxxxxx; yang@xxxxxxxxxx; =
=3D
si-list@xxxxxxxxxxxxx
=3DB3=3DAD=3DCB=3DCD: liuweidong@xxxxxxxxxx
=3DD6=3DF7=3DCC=3DE2: RE: [SI-LIST] Re: Buffer delay

Hello, Yan Hang,

IBIS and SPICE do not have the same Time=3D3D0 reference, due to the way =
=3D
SI
tools trigger I/O inputs.  This means that there is a time offset =3D
between
the two waveforms.

This offset can be corrected for by simulating the load [Vmeas, Rref, =
=3D
Cref].
This delay offset can then be used to adjust the delay in other =3D
simulations.
Many SI tools have automated this process.

A good paper on this is http://pcdandm.com/cms/content/view/2800/95/.  =
=3D
There
is also a HyperLynx Application Note, referenced in that paper.

Best regards,
Lynne

"IBIS training when you need it, where you need it."

Dr. Lynne Green
Green Streak Programs
http://www.greenstreakprograms.com
425-788-0412
lgreen22@xxxxxxxxxxxxxx


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
=3D
On
Behalf Of raj singh
Sent: Friday, November 17, 2006 1:34 AM
To: yang@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
Cc: liuweidong@xxxxxxxxxx
Subject: [SI-LIST] Re: Buffer delay

Hspice delays should be accurate and in general more than ibis. Better =
=3D
to
use ibis only for SI sims and not for timing.
  =3D20
  regards
  Raj
yan hang <yang@xxxxxxxxxx> wrote:
 =3D20
Hi All,
Now I do some board timing simulations . I got the hspice =3D3D model =
and
=3D
ibis
model for same buffer. Then I set a test fixture(Ex.
Cref=3D3D3D15pf,Rref=3D3D3D1E6,Vref=3D3D3D3.3V),I contrast the =
simulation =3D
result of =3D3D
buffer dealy using hspice model and ibis model. I found there is a =3D
little
big diffrence between them.
So when translate hspice model to ibis model,how to consider about the
buffer deley issue? =3D3D20 Should I trust the buffer delay value from =
=3D
ibis
model =3D3D simulation?

Best Regards.

Yan Hang
Huawei Technology
086-21=3D3DA3=3D3DAD68644808=3D3DA3=3D3DAD24043





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