Having accurate timing in an IBIS file, say from the input to a buffer to the die pad for that buffer on the silicon is interesting. It is also fraught with pitfalls. If you are interested in _all_ the delays in the system, you need to draw the line somewhere. While not going into where to place the responsibility for complete timing analysis of a circuit, there are some things in IBIS that you need to be careful with. If your IBIS file contains timing information for the entire time from input to the buffer to the end of the transition and ringing at the end of the transient event you wind up with a whole lot of time points that are meaningless. I have seen some ECL driver models where, because of the decimation of the actual transition data to fit into a reasonable size table, the actual event had only about 5 points. That amount of data for the simulator is sadly insufficient. If you look at a plot of the data there is nearly nothing to look at. =20 Also, if you are doing a Spice Simulation, with an IBIS model like that, there is a lot of time going to waste in the simulation because each time step is analyzed while nothing is happening. This sort of thing could lead to a good relaxed day while you are waiting for the simulation to run. On the other hand it is fun to get the job done and have some time at home with the family. dav0 David Lieby -----Original Message----- From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of zheng qi Sent: Monday, November 20, 2006 5:17 PM To: michael.mirmak@xxxxxxxxx Cc: si-list@xxxxxxxxxxxxx Subject: [SI-LIST] Re: Buffer delay I would agree with Mirmak michael about accuracy of IBIS vs Spice and on 2006 shanghai ibis summit i had shown some evaluation result , But..but as to timing issues i have the same question as yan hang mentioned and i also brought it on 2005 shenzhen ibis summit . there i adviced that when doing more tight timing analysis maybe core to core timing is more suitable. The problem here is when comparing with IBIS and Hspice model output that the t waveform under test load condition does exist a timing offset,and sometimes up to 1ns. So if the model had well-constructed as Michael Mirmak said , everything will be OK , But the fact is that these type of 'good ' model seems does not exist , is it true ?? If it is, In what extent does we can believe with the timing analysis of IBIS ? Best regards zheng qi qzheng@xxxxxxxxxxxxxxxx Best Regards qzheng ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: =20 //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu =20 ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu