[SI-LIST] Re: Buffer delay
- From: "Mirmak, Michael" <michael.mirmak@xxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Fri, 17 Nov 2006 10:54:16 -0800
All,
I would disagree somewhat with the conclusions regarding accuracy and
IBIS vs. SPICE models.
We must be very careful in how the words "buffer delay" are being used
here. For system analyses, many tools define "buffer delay" as the time
elapsed between the start of *simulation* and the crossing of a defined
measurement voltage, using a defined measurement load. For a
well-constructed IBIS model, even using traditional V-t and I-V tables,
excellent correlation to SPICE transistor-level models may be obtained
for buffer delay in this sense. As a result, IBIS could be -- and is --
used for system timing analysis where the timing equations use buffer
delay.
Timings for driver outputs relative to an incoming clock signal -- for
example, "Tvalid" or "Tco" (Time clock to out) -- could not be directly
simulated under traditional IBIS, as the format does not include the
data path from the incoming clock node to the driver, to "latch" the
signal out. =20
Advanced IBIS models, such as those under IBIS 4.1 and 4.2 using
multi-lingual extensions, may contain these driver clock-to-out
connections and paths, should the model author choose to include them.
A direct comparison of clock-to-out waveforms between this kind of
advanced IBIS model and a SPICE transistor model may then be obtained.
I hope this helps!
- Michael Mirmak
Intel Corp.
Chair, EIA IBIS Open Forum
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of raj singh
Sent: Friday, November 17, 2006 01:34
To: yang@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
Cc: liuweidong@xxxxxxxxxx
Subject: [SI-LIST] Re: Buffer delay
Hspice delays should be accurate and in general more than ibis. Better
to use ibis only for SI sims and not for timing.
=20
regards
Raj
yan hang <yang@xxxxxxxxxx> wrote:
=20
Hi All,
Now I do some board timing simulations . I got the hspice model and ibis
model for same buffer. Then I set a test fixture(Ex.
Cref=3D15pf,Rref=3D1E6,Vref=3D3.3V),I contrast the simulation result of =
buffer
delay using hspice model and ibis model. I found there is a little big
diffrence between them.
So when translate hspice model to ibis model,how to consider about the
buffer deley issue?=20
Should I trust the buffer delay value from ibis model simulation?
Best Regards.
Yan Hang
Huawei Technology
086-21=3DA3=3DAD68644808=3DA3=3DAD24043
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