Posts for si-list, 11-2006

Browse: Last Month: 10-2006 Main Archive Page Next Month: 12-2006

» [SI-LIST] Re: DDR2 IMPEDANCE -
» [SI-LIST] DDR2 IMPEDANCE -
» [SI-LIST] Package signal integrity position at NXP -
» [SI-LIST] Electrical Engineering Manger -
» [SI-LIST] Re: trace length matching -
» [SI-LIST] Re: trace length matching -
» [SI-LIST] use of PVT corner models for various speed-grades -
» [SI-LIST] trace length matching -
» [SI-LIST] Re: Slew Rate Calculation -
» [SI-LIST] Re: Slew Rate Calculation -
» [SI-LIST] Re: Slew Rate Calculation -
» [SI-LIST] Re: Slew Rate Calculation -
» [SI-LIST] Re: Slew Rate Calculation -
» [SI-LIST] Re: Slew Rate Calculation -
» [SI-LIST] Re: Slew Rate Calculation -
» [SI-LIST] Re: Slew Rate Calculation -
» [SI-LIST] Re: R: Re: R: digital core model -
» [SI-LIST] Re: ESD simulations -
» [SI-LIST] Re: R: Re: R: digital core model -
» [SI-LIST] R: Re: R: digital core model -
» [SI-LIST] Re: R: digital core model -
» [SI-LIST] R: digital core model -
» [SI-LIST] Re: ESD simulations -
» [SI-LIST] digital core model -
» [SI-LIST] Re: PICMG3.1 : is length matching really necessary? -
» [SI-LIST] Re: ESD simulations -
» [SI-LIST] Re: ESD simulations -
» [SI-LIST] Patents on backplane, via design, misc... -
» [SI-LIST] Re: About S2ibis2 -
» [SI-LIST] Re: About S2ibis2 -
» [SI-LIST] About S2ibis2 -
» [SI-LIST] Re: ESD simulations -
» [SI-LIST] si-list web site address change -
» [SI-LIST] Re: hspi new release -
» [SI-LIST] hspi new release -
» [SI-LIST] ESD simulations -
» [SI-LIST] Re: Slew Rate Calculation -
» [SI-LIST] Re: Thick vs. thin diff. pairs -
» [SI-LIST] Re: Thick vs. thin diff. pairs -
» [SI-LIST] Re: Thick vs. thin diff. pairs -
» [SI-LIST] Test Mail Please Ignore -
» [SI-LIST] Slew Rate Calculation -
» [SI-LIST] Re: Thick vs. thin diff. pairs -
» [SI-LIST] PICMG3.1 : is length matching really necessary? -
» [SI-LIST] Re: Trace width for 20 amps -
» [SI-LIST] Trace width for 20 amps -
» [SI-LIST] Differential IBIS model (with pre-emphasis) generation -
» [SI-LIST] Re: Trace impedance -
» [SI-LIST] Re: A New Open Source SI Analysis Tool -
» [SI-LIST] Re: A New Open Source SI Analysis Tool -
» [SI-LIST] A New Open Source SI Analysis Tool -
» [SI-LIST] Re: Trace impedance -
» [SI-LIST] Re: Why no timing model available unitl now? -
» [SI-LIST] Re: Trace impedance -
» [SI-LIST] Re: Statistical Timing Budgets Analysis -
» [SI-LIST] Why no timing model available unitl now? -
» [SI-LIST] Re: Trace impedance -
» [SI-LIST] Re: Thick vs. thin diff. pairs -
» [SI-LIST] SI job posting, Celestica, Ottawa ON -
» [SI-LIST] Re: Buffer delay -
» [SI-LIST] Re: Buffer delay -
» [SI-LIST] Re: Trace impedance -
» [SI-LIST] Statistical Timing Budgets Analysis -
» [SI-LIST] Re: Trace impedance -
» [SI-LIST] 回复:Statistical Timing Budgets Analysis -
» [SI-LIST] Re: Trace impedance -
» [SI-LIST] Re: Buffer delay -
» [SI-LIST] Trace impedance -
» [SI-LIST] Re: Thick vs. thin diff. pairs -
» [SI-LIST] Re: Buffer delay -
» [SI-LIST] Re: Buffer delay -
» [SI-LIST] Re: Buffer delay -
» [SI-LIST] Re: Buffer delay -
» [SI-LIST] Re: Thick vs. thin diff. pairs -
» [SI-LIST] Re: Thick vs. thin diff. pairs -
» [SI-LIST] Re: Thick vs. thin diff. pairs -
» [SI-LIST] Re: Thick vs. thin diff. pairs -
» [SI-LIST] Re: Thick vs. thin diff. pairs -
» [SI-LIST] Re: Thick vs. thin diff. pairs -
» [SI-LIST] Thick vs. thin diff. pairs -
» [SI-LIST] Re: About S2ibis2 -
» [SI-LIST] Re: Buffer delay -
» [SI-LIST] Re: Buffer delay -
» [SI-LIST] About S2ibis2 -
» [SI-LIST] noise/emi getting into signal measurements -
» [SI-LIST] Re: Buffer delay -
» [SI-LIST] Re: Buffer delay -
» [SI-LIST] Re: immediate opening for Board Design Lead -
» [SI-LIST] Re: Fiber transceiver assemblies, fully assembled? -
» [SI-LIST] Re: Buffer delay -
» [SI-LIST] Buffer delay -
» [SI-LIST] Re: A question for the instrument guys on TDR and TDT -
» [SI-LIST] immediate opening for Board Design Lead -
» [SI-LIST] Re: Fiber transceiver assemblies, fully assembled? -
» [SI-LIST] Re: How to generate IBIS model -
» [SI-LIST] ddr2 2 sodimm design - clk to add&control signals metcing -
» [SI-LIST] Fiber transceiver assemblies, fully assembled? -
» [SI-LIST] Re: Package SI -
» [SI-LIST] How to generate IBIS model -
» [SI-LIST] Series resistor b/w grounds -
» [SI-LIST] Re: A question for the instrument guys on TDR and TDT -
» [SI-LIST] Re: A question for the instrument guys on TDR and TDT -
» [SI-LIST] Re: A question for the instrument guys on TDR and TDT -
» [SI-LIST] Re: A question for the instrument guys on TDR and TDT -
» [SI-LIST] Re: A question for the instrument guys on TDR and TDT -
» [SI-LIST] UNSUBSCRIBE -
» [SI-LIST] COMMANDS -
» [SI-LIST] Recall: EMC engineer position open in Shanghai, China -
» [SI-LIST] EMC engineer position open in Shanghai, China -
» [SI-LIST] EMI/EMC Seminar -
» [SI-LIST] Re: Fwd: Re: Copper pours on a 2-layer PCB -
» [SI-LIST] Fwd: Re: Copper pours on a 2-layer PCB -
» [SI-LIST] Re: Copper pours on a 2-layer PCB -
» [SI-LIST] Re: Copper pours on a 2-layer PCB -
» [SI-LIST] Package SI -
» [SI-LIST] Novel chip-to-chip interconnect hits 10 Gbit/s -
» [SI-LIST] Copper pours on a 2-layer PCB -
» [SI-LIST] Re: Conductor loss or Dielectric loss -
» [SI-LIST] Re: Conductor loss or Dielectric loss -
» [SI-LIST] Re: Conductor loss or Dielectric loss -
» [SI-LIST] Re: Conductor loss or Dielectric loss -
» [SI-LIST] Job opening: Signal Integrity Engineer -
» [SI-LIST] Re: Trace length problem -
» [SI-LIST] Hi Test -
» [SI-LIST] Trace length problem -
» [SI-LIST] Re: Conductor loss or Dielectric loss -
» [SI-LIST] Conductor loss or Dielectric loss -
» [SI-LIST] unsubscribe -
» [SI-LIST] RF shapes behaviour at high speeds -
» [SI-LIST] Re: How to evaluate IBIS model -
» [SI-LIST] Re: How to evaluate IBIS model -
» [SI-LIST] How to evaluate IBIS model -
» [SI-LIST] Short-term Consulting -
» [SI-LIST] Board/DVT project in San Jose, CA -
» [SI-LIST] User2User 2007 Call4Papers ... -
» [SI-LIST] Signal and Power Integrity Applications Engineer Vacancy -
» [SI-LIST] Re: A question for the instrument guys on TDR and TDT -
» [SI-LIST] Re: DDR Interface Topology -
» [SI-LIST] Re: A question for the instrument guys on TDR and TDT -
» [SI-LIST] Re: A question for the instrument guys on TDR and TDT -
» [SI-LIST] Re: How to simulate ESD test of one chip CMOS chip -
» [SI-LIST] Re: A question for the instrument guys on TDR and TDT -
» [SI-LIST] Re: Heatsink electrical isolation -
» [SI-LIST] TEST MAIL -
» [SI-LIST] Re: A question for the instrument guys on TDR and TDT -
» [SI-LIST] SSO corner cases -
» [SI-LIST] hai test mail -
» [SI-LIST] Hi -
» [SI-LIST] Re: A question for the instrument guys on TDR and TDT -
» [SI-LIST] Re: A question for the instrument guys on TDR and TDT -
» [SI-LIST] Re: A question for the instrument guys on TDR and TDT -
» [SI-LIST] Re: A question for the instrument guys on TDR and TDT -
» [SI-LIST] Re: A question for the instrument guys on TDR and TDT -
» [SI-LIST] Re: A question for the instrument guys on TDR and TDT -
» [SI-LIST] Re: DDR Interface Topology -
» [SI-LIST] AMD Hiring SI Engineer -
» [SI-LIST] A question for the instrument guys on TDR and TDT -
» [SI-LIST] Signal Integrity Position - Andover MA -
» [SI-LIST] How to simulate ESD test of one chip CMOS chip -
» [SI-LIST] one problem about ESD simulation -
» [SI-LIST] Re: DDR Interface Topology -
» [SI-LIST] DDR Interface Topology -
» [SI-LIST] Leading Insight Northwest - Ansoft Application Workship - Nov. 14 in Beaverton, OR -
» [SI-LIST] flip chip model for DDR3 -
» [SI-LIST] Electrical Design of Advanced Packaging and Systems (EDAPS) -
» [SI-LIST] Electrical Design of Advanced Packaging and Systems (EDAPS) -