[SI-LIST] Re: Buffer delay
- From: "Lynne D. Green" <lgreen22@xxxxxxxxxxxxxx>
- To: <yang@xxxxxxxxxx>
- Date: Sun, 19 Nov 2006 23:15:23 -0800
Hello, Yan Hang,
Are you asking about the timing offset for the standard load (Vmeas, Rref,
Cref) in IBIS against SPICE? The time offset issue will arise in hardware
testing (also required for IQ=3 models).
This check requires two things: (1) making sure the waveforms and delay to
Vmeas are correct after adjusting for the time offset, and (2) making sure
all Waveform tables for a model have the same Time=0 reference, and the
delay to Vmeas in the tables is much shorter than a clock period.
More information on checking waveforms and the IBIS Figure of Merit for
waveform comparisons can be found at
http://www.vhdl.org/pub/ibis/accuracy/handbook.pdf
Best regards,
Lynne
"IBIS training when you need it, where you need it."
Dr. Lynne Green
Green Streak Programs
http://www.greenstreakprograms.com
425-788-0412
lgreen22@xxxxxxxxxxxxxx
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of yan hang
Sent: Sunday, November 19, 2006 8:32 PM
To: si-list@xxxxxxxxxxxxx
Cc: liuweidong@xxxxxxxxxx
Subject: [SI-LIST] Re: Buffer delay
Hello Lynne & Michael ,
In the "IBIS QUALITY SPECIFICATION ", it defined that the IQ3=20
level--the model data for timing analysis has been checked. If there is = a
time of offset between the two waveforms(IBIS &HSPICE),shoule we say the
model can not pass the IQ3?
When we use hspice model to create ibis model ,do we must check the = offset
and correct it?
Best Regards,
Yan Hang
Huawei Technology
Shanghai Research Institute
Interconnection Dept.,R&D
Tel =A3=AB862168644808=A3=AD24043
-----=D3=CA=BC=FE=D4=AD=BC=FE-----
=B7=A2=BC=FE=C8=CB: Lynne D. Green [mailto:lgreen22@xxxxxxxxxxxxxx]=20
=B7=A2=CB=CD=CA=B1=BC=E4: 2006=C4=EA11=D4=C218=C8=D5 3:36
=CA=D5=BC=FE=C8=CB: forsilist@xxxxxxxxx; yang@xxxxxxxxxx; =
si-list@xxxxxxxxxxxxx
=B3=AD=CB=CD: liuweidong@xxxxxxxxxx
=D6=F7=CC=E2: RE: [SI-LIST] Re: Buffer delay
Hello, Yan Hang,
IBIS and SPICE do not have the same Time=3D0 reference, due to the way = SI
tools trigger I/O inputs. This means that there is a time offset = between
the two waveforms.
This offset can be corrected for by simulating the load [Vmeas, Rref, =
Cref].
This delay offset can then be used to adjust the delay in other =
simulations.
Many SI tools have automated this process.
A good paper on this is http://pcdandm.com/cms/content/view/2800/95/. =
There is also a HyperLynx Application Note, referenced in that paper.
Best regards,
Lynne
"IBIS training when you need it, where you need it."
Dr. Lynne Green
Green Streak Programs
http://www.greenstreakprograms.com
425-788-0412
lgreen22@xxxxxxxxxxxxxx
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
On Behalf Of raj singh
Sent: Friday, November 17, 2006 1:34 AM
To: yang@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
Cc: liuweidong@xxxxxxxxxx
Subject: [SI-LIST] Re: Buffer delay
Hspice delays should be accurate and in general more than ibis. Better = to
use ibis only for SI sims and not for timing.
=20
regards
Raj
yan hang <yang@xxxxxxxxxx> wrote:
=20
Hi All,
Now I do some board timing simulations . I got the hspice =3D model and =
ibis model for same buffer. Then I set a test fixture(Ex.
Cref=3D3D15pf,Rref=3D3D1E6,Vref=3D3D3.3V),I contrast the simulation = result
of =3D buffer dealy using hspice model and ibis model. I found there is a =
little big diffrence between them.
So when translate hspice model to ibis model,how to consider about the
buffer deley issue? =3D20 Should I trust the buffer delay value from = ibis
model =3D simulation?
Best Regards.
Yan Hang
Huawei Technology
086-21=3DA3=3DAD68644808=3DA3=3DAD24043
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