[SI-LIST] Re: reference plane cutout under DC blocking capacitor pads
- From: "Yuriy Shlepnev" <shlepnev@xxxxxxxxxxxxx>
- To: <bala89si@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Tue, 19 Nov 2013 11:32:31 -0800
Balaji,
Considering the return path, simple analysis of cross-sections with and
without cutout and with and without the additional reference plane in a
field solver can explain the role of the distant planes and were the
currents are. In fact, such analysis of the cross-sections may be the
starting point of the capacitor or connector pad design. First task may be
to maintain the target characteristic impedance in all cross-sections along
the signal propagation path. Something similar to done at
www.simberian.com/AppNotes/Shlepnev_DesignInsights_FRSI_Oct3_2013.pdf - see
from slide 25. The next task would be the 3D analysis of the complete
transition and minimization of the reflection and possible coupling to
traces in adjacent layers or to parallel plane cavity. Note, that the
cut-outs in the return path may provide strong coupling to the cavity below
and such cavity must be confined (localized) to avoid SI and EMI problems as
demonstrated on slides 26-28 at the FRSI presentation referenced above.
Best regards,
Yuriy
Yuriy Shlepnev, Ph.D.
President, Simberian Inc.
3030 S Torrey Pines Dr. Las Vegas, NV 89146, USA
Office +1-702-876-2882; Fax +1-702-482-7903
Cell +1-206-409-2368; Virtual +1-408-627-7706
Skype: shlepnev
www.simberian.com
Simbeor - Accurate, Fast, Easy and Affordable Electromagnetic Signal
Integrity Software
2010 and 2011 DesignVision Award Winner
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Balaji G
Sent: Monday, November 18, 2013 6:26 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] reference plane cutout under DC blocking capacitor pads
Hi all,
I believe reference plane cutouts under the DC blocking capacitor pads
for high speed signals help us minimizing the extra capacitance created
between pads and planes and reduces the impedance discontinuity.
This means that the pad should refer the farther ground/power as
reference (20 mils away from signal layer). Is that means we need to
engineer the layers under the cutouts? Say we should move the traces away
which are going under the cutout region in the signal layer directly under
high speed reference plane.
Also, in certain application notes, I got to look at a recommendation of
adding ground stitching vias near the pads to provide current return path.
If the signals are high speed (12Gbps), I believe the returns would prefer
to take a loop around the cutout region in the immediate reference plane
rather taking a loop through the ground stitching vias. Can you provide your
thoughts on this?
Regards,
Balaji
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