[SI-LIST] Re: reference plane cutout under DC blocking capacitor pads
- From: steve weir <weirsi@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 18 Nov 2013 19:31:47 -0800
Yes, the projection of the voided ground region should be treated as a
keep-out region on signal layers.
It is not a matter of either / or. Stitching vias create reflection
boundaries. The energy was and remains mostly in the dielectric.
Steve.
On 11/18/2013 6:26 PM, Balaji G wrote:
> Hi all,
> I believe reference plane cutouts under the DC blocking capacitor pads
> for high speed signals help us minimizing the extra capacitance created
> between pads and planes and reduces the impedance discontinuity.
>
> This means that the pad should refer the farther ground/power as
> reference (20 mils away from signal layer). Is that means we need to
> engineer the layers under the cutouts? Say we should move the traces away
> which are going under the cutout region in the signal layer directly under
> high speed reference plane.
>
> Also, in certain application notes, I got to look at a recommendation of
> adding ground stitching vias near the pads to provide current return path.
> If the signals are high speed (12Gbps), I believe the returns would prefer
> to take a loop around the cutout region in the immediate reference plane
> rather taking a loop through the ground stitching vias. Can you provide
> your thoughts on this?
>
>
> Regards,
> Balaji
>
>
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