[SI-LIST] Re: reference plane cutout under DC blocking capacitor pads
- From: steve weir <weirsi@xxxxxxxxxx>
- To: si-list <si-list@xxxxxxxxxxxxx>
- Date: Tue, 19 Nov 2013 01:55:14 -0800
The closest filled area underneath the capacitor and immediately
surrounding area defines most of the parasitic capacitance. Signals
that reside completely beneath the fill area are shielded by it. If you
use more than one circuit node in the return path, then you inject
energy between between the various nodes that compose the return path.
Whether that will be tolerable or not depends on the parameters of the
specific design.
The safe thing to do is follow the advice of renowned former First Lady
and signal integrity expert Nancy Reagan: "Just say no to divided
returns under glass stupid." (When solving SI problems, the First Lady
often became emotionally agitated and was not always very diplomatic.
People attribute her curt language to frustration with having only a
PDP-11 for her SI work.)
Where the signal being AC coupled references Vss approaching and leaving
the coupling capacitor that would mean voiding all layers between the
capacitor and the nearest unvoided Vss layer or filled and stitched Vss
polygon. The simple trace over plane structure changes to a box like
structure in the vicinity of the capacitor and pads in order to keep the
impedance uniform and the signal energy contained and isolated from
energy from other signals.
View with fixed width font:
signal ------ | capacitor | ------------------- signal
Energy Energy
------------| |---------------- Vss
---- sig | Energy | sig ----
---- sig | | sig ----
------------------------------------------------------- Vss
In this simplified view, the signal energy is contained by metal first
in the simple microstrip structure at the very left and very right, and
then in the more complex box-like structure formed by the coupling
capacitor on the top, and Vss stitch for the vertical and bottom walls
in the middle.
Steve.
On 11/19/2013 1:07 AM, Balaji G wrote:
> Hi Steve,
>
> Can you please provide a small clarification here. You asked me to
> have voids in all signal layers. Say, if there is a power layer after
> the signal layer. we will create a void in signal layer, then, should
> we also need to create the void in the power layer or we can leave as
> it as solid?. I was thinking the power layer can also provide the
> return for this current coupled through the small capacitance. If it
> is not, my understanding will be wrong.
>
> Regards,
> Balaji
>
>
> On Tue, Nov 19, 2013 at 11:23 AM, Balaji G <bala89si@xxxxxxxxx
> <mailto:bala89si@xxxxxxxxx>> wrote:
>
> Hi Steve,
>
> Thank you very much. Your second point gave me a lot of insight!.
>
> Regards,
> Balaji
>
>
> On Tue, Nov 19, 2013 at 9:01 AM, steve weir <weirsi@xxxxxxxxxx
> <mailto:weirsi@xxxxxxxxxx>> wrote:
>
> Yes, the projection of the voided ground region should be
> treated as a
> keep-out region on signal layers.
>
> It is not a matter of either / or. Stitching vias create
> reflection
> boundaries. The energy was and remains mostly in the dielectric.
>
> Steve.
> On 11/18/2013 6:26 PM, Balaji G wrote:
> > Hi all,
> > I believe reference plane cutouts under the DC blocking
> capacitor pads
> > for high speed signals help us minimizing the extra
> capacitance created
> > between pads and planes and reduces the impedance discontinuity.
> >
> > This means that the pad should refer the farther
> ground/power as
> > reference (20 mils away from signal layer). Is that means we
> need to
> > engineer the layers under the cutouts? Say we should move
> the traces away
> > which are going under the cutout region in the signal layer
> directly under
> > high speed reference plane.
> >
> > Also, in certain application notes, I got to look at a
> recommendation of
> > adding ground stitching vias near the pads to provide
> current return path.
> > If the signals are high speed (12Gbps), I believe the
> returns would prefer
> > to take a loop around the cutout region in the immediate
> reference plane
> > rather taking a loop through the ground stitching vias. Can
> you provide
> > your thoughts on this?
> >
> >
> > Regards,
> > Balaji
> >
> >
> >
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> --
> Steve Weir
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--
Steve Weir
IPBLOX, LLC
1580 Grand Point Way
MS 34689
Reno, NV 89523-9998
www.ipblox.com
(775) 299-4236 Business
(866) 675-4630 Toll-free
(707) 780-1951 Fax
All contents Copyright (c)2013 IPBLOX, LLC. All Rights Reserved.
This e-mail may contain confidential material.
If you are not the intended recipient, please destroy all records
and notify the sender.
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