[SI-LIST] Re: reference plane cutout under DC blocking capacitor pads

  • From: "Antonis Orphanou" <orphanou@xxxxxxxxxxxx>
  • To: "bala89si@xxxxxxxxx" <bala89si@xxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
  • Date: Tue, 19 Nov 2013 19:02:21 +0000

For the most part the capacitor pad is rather short to be considered a 
significant discontinuity. However when you try to make it a 50 ohm transition 
you have to open up the planes underneath. Usually there are plenty of ground 
vias around the cut-up area so the need for extra stitching might be little bit 
excessive but a safe practice.



-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
Behalf Of Balaji G
Sent: Monday, November 18, 2013 6:26 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] reference plane cutout under DC blocking capacitor pads

Hi all,
   I believe reference plane cutouts under the DC blocking capacitor pads
for high speed signals help us minimizing the extra capacitance created
between pads and planes and reduces the impedance discontinuity.

    This means that the pad should refer the farther ground/power as
reference (20 mils away from signal layer). Is that means we need to
engineer the layers under the cutouts? Say we should move the traces away
which are going under the cutout region in the signal layer directly under
high speed reference plane.

   Also, in certain application notes, I got to look at a recommendation of
adding ground stitching vias near the pads to provide current return path.
If the signals are high speed (12Gbps), I believe the returns would prefer
to take a loop around the cutout region in the immediate reference plane
rather taking a loop through the ground stitching vias. Can you provide
your thoughts on this?


Regards,
Balaji


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