[SI-LIST] Re: reference plane cutout under DC blocking capacitor pads
- From: "Antonis Orphanou" <orphanou@xxxxxxxxxxxx>
- To: "Scott McMorrow" <scott@xxxxxxxxxxxxx>
- Date: Tue, 19 Nov 2013 23:02:14 +0000
Hello Scott, thanks for your response.
Your point is correct and I absolutely agree with you. Cutting the planes below
the pad is a safe practice and I use that myself....
However I do not agree that an un-cleared pad can be catastrophic to the
bandwidth. Yes there will be some return loss compromise but that's not a do or
die scenario.
Regards
Antonis.
From: Scott McMorrow [mailto:scott@xxxxxxxxxxxxx]
Sent: Tuesday, November 19, 2013 1:03 PM
To: Antonis Orphanou
Cc: si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: reference plane cutout under DC blocking capacitor
pads
Antonis
You are correct, the original question concerned capacitor pads. From my point
of view, the pads and the capacitor body come together as a unit. It is
usually better to optimize the cutout for all pads and capacitors in a
differential DC block simultaneously. Extra points for modeling the plates
inside of the capacitor. Done right, the solution can have extremely wide
bandwidth and avoid sharp cutoff. I generally try to keep as much energy out of
the PCB cavity as possible, contain that energy which does leak in, and keep
slow wave capacitor resonance from being strongly excited.
Scott
On Tue, Nov 19, 2013 at 2:45 PM, Antonis Orphanou
<orphanou@xxxxxxxxxxxx<mailto:orphanou@xxxxxxxxxxxx>> wrote:
Hello scott,
I was talking about the capacitor pcb-pads not the capacitor itself. I thought
that what the discussion was about :) .. ?
regards
Antonis
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx<mailto:si-list-bounce@xxxxxxxxxxxxx>
[mailto:si-list-bounce@xxxxxxxxxxxxx<mailto:si-list-bounce@xxxxxxxxxxxxx>] On
Behalf Of Scott McMorrow
Sent: Tuesday, November 19, 2013 11:40 AM
Cc: si-list@xxxxxxxxxxxxx<mailto:si-list@xxxxxxxxxxxxx>
Subject: [SI-LIST] Re: reference plane cutout under DC blocking capacitor pads
Antonis
with all due respect, a capacitor is not an insignificant discontinuity.
Given the pad, body, end cap, and the plate structure for a 0402 MLCC
capacitor, it exhibits a low impedance discontinuity, with a cutoff
frequency around 10-15 GHz, without some compensation structures built into
the planes. In many designs that I've seen there are no ground stitching
capacitors between a multitude of DC blocking capacitors, and as a result,
excessive crosstalk exists. I've seen quite a few designs where the
capacitors are arranged in a linear array at minimum spacing, which ends
allowing coupling of the body sidewalls.
Vias correctly placed will serve to minimize crosstalk and contain the
common modes that propagate due to signal skew. Common mode conversion
near the receiver can have some disastrous multi-aggressor crosstalk
peaking implications.
regards,
Scott
On Tue, Nov 19, 2013 at 2:02 PM, Antonis Orphanou
<orphanou@xxxxxxxxxxxx<mailto:orphanou@xxxxxxxxxxxx>>wrote:
> For the most part the capacitor pad is rather short to be considered a
> significant discontinuity. However when you try to make it a 50 ohm
> transition you have to open up the planes underneath. Usually there are
> plenty of ground vias around the cut-up area so the need for extra
> stitching might be little bit excessive but a safe practice.
>
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx<mailto:si-list-bounce@xxxxxxxxxxxxx>
> [mailto:si-list-bounce@xxxxxxxxxxxxx<mailto:si-list-bounce@xxxxxxxxxxxxx>]
> On Behalf Of Balaji G
> Sent: Monday, November 18, 2013 6:26 PM
> To: si-list@xxxxxxxxxxxxx<mailto:si-list@xxxxxxxxxxxxx>
> Subject: [SI-LIST] reference plane cutout under DC blocking capacitor pads
>
> Hi all,
> I believe reference plane cutouts under the DC blocking capacitor pads
> for high speed signals help us minimizing the extra capacitance created
> between pads and planes and reduces the impedance discontinuity.
>
> This means that the pad should refer the farther ground/power as
> reference (20 mils away from signal layer). Is that means we need to
> engineer the layers under the cutouts? Say we should move the traces away
> which are going under the cutout region in the signal layer directly under
> high speed reference plane.
>
> Also, in certain application notes, I got to look at a recommendation of
> adding ground stitching vias near the pads to provide current return path.
> If the signals are high speed (12Gbps), I believe the returns would prefer
> to take a loop around the cutout region in the immediate reference plane
> rather taking a loop through the ground stitching vias. Can you provide
> your thoughts on this?
>
>
> Regards,
> Balaji
>
>
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--
Scott McMorrow
Teraspeed Consulting Group LLC
16 Stormy Brook Rd
Falmouth, ME 04105
(401) 284-1827 Business
http://www.teraspeed.com
Teraspeed(r) is the registered service mark of
Teraspeed Consulting Group LLC
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Teraspeed Consulting Group LLC
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(401) 284-1827 Business
http://www.teraspeed.com
Teraspeed(r) is the registered service mark of
Teraspeed Consulting Group LLC
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