[SI-LIST] Re: pcb stackup
- From: "mkhusid" <mkhusid@xxxxxxxxxx>
- To: <james.f.peterson@xxxxxxxxxxxxx>, <humps@xxxxxxx>,<si-list@xxxxxxxxxxxxx>
- Date: Wed, 18 Jun 2003 11:37:42 -0400
I second Matt here. I think a thin core which allows for strong coupling
between power and ground will help much with the power noise and will
alleviate the need for the second nearby ground plane.
Also, are the grounds on top and bottom layers required? In my
experience, those grounds never become real planes because of components
on both sides of the board. As a result, the planes are segmented into
smaller chunks and may create more EMI hazards than what they were
supposed to solve.
Mike
----------------------------------------------------------------
Michael Khusid
Ansoft Corporation
SI/HF Application Engineer
25 Burlington Mall Road, 6th floor
Burlington, MA 01803-4100
Tel 781-229-8900 Ext. 34
Fax 781-229-8624
---------------------http://www.ansoft.com ---------------------
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Matthew Humphreys
Sent: Wednesday, June 18, 2003 11:16 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: pcb stackup
Hi,
The proposed stackup will indeed reduce the noise on your 3.3v plane.
However, instead of surrounding the plane with two gnd planes, I would
suggest adding a second pwr/gnd pair to the stackup to maintain
symmetry.
Make sure you couple the pwr/gnd pairs as closely as possible. I
usually
use 4 mil cores for pwr/gnd pairs. If you need 6 routing layers, I
would
probably try to do the following;
1) G
2) S
3) S
4) +3.3V
5) G
6) S
7) S
8) +3.3V
9) G
10)S
11)S
12)G
I wouldn't be surprised if someone else has a better idea, which is why
is
subscribe.
Matt
-----Original Message-----
From: Peterson, James F (FL51) [mailto:james.f.peterson@xxxxxxxxxxxxx]
Sent: Wednesday, June 18, 2003 6:56 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] pcb stackup
a typical stackup at our company might look like this:
1) G
2) S
3) S
4) +3.3V
5) S
6) S
7) G
8) S
9) S
10)G
note that we use layer 4 (+3.3V) as a reference plane.
an alternate stackup is now being pushed here that doesn't allow this.
the
alternative approach says that this puts too much noise in the +3.3V
plane.
that we should surround the +3.3V plane with ground planes, as shown
below :
1) G
2) S
3) S
4) G
5) +3.3
6) G
7) S
8) S
9) G
10)S
11)S
12)G
Comments?
thanks,
Jim Peterson
Honeywell
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