[SI-LIST] Re: pcb stackup
- From: "npischl" <npischl@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 18 Jun 2003 20:35:11 -0000
Yes, you may have EMI concern if you route adjacent to the power
plane. However, it is highly dependent on the many factors. The most
important ones (not the only ones) would be the impedance and
consequentially RF voltage between the power and logic 0 return
planes and how the PCB is connected to the enclosure. In best case it
won't matter if you do it, in worst case it will make a big
difference, especially if the I/O routing is adjacent to the Vcc
planes.
I tried to describe it in a technical information document EMC-TI100,
section on PCB stackup selection, published by Broadcom. It is only
available to Broadcom customers who have access to their
documentation web site. Since Broadcom provides communications
semiconductors to many companies, you might have access to the
documentation. Ask your rep.
Neven
--- In si-list@xxxxxxxxxxxxxxx, james.f.peterson@xxxx wrote:
> not a bad question at all.
> it's a good point....we usually move everything down one layer to
allow for
> that.
>
> my primary question to all is : do we really have to surround our
+3.3V
> planes with gnds?
> is there an emi concern with using the +3.3v plane as a reference
plane?
>
> thanks again,
> Jim
>
> -----Original Message-----
> From: Jon Powell [mailto:jonpowell@xxxx]
> Sent: Wednesday, June 18, 2003 11:59 AM
> To: humps@xxxx; si-list@xxxx
> Subject: [SI-LIST] Re: pcb stackup
>
>
> My (perhaps ignorant) question of the week.
>
> If your top and bottom layers are GND (and presumably meant as a
return
> signal or reference plane), how do you attach any kind of complex
IC's
> without perforating the plane to uselessness?
>
> jon
>
>
> -----Original Message-----
> From: si-list-bounce@xxxx
> [mailto:si-list-bounce@xxxx]On Behalf Of Matthew Humphreys
> Sent: Wednesday, June 18, 2003 8:16 AM
> To: si-list@xxxx
> Subject: [SI-LIST] Re: pcb stackup
>
>
> Hi,
>
> The proposed stackup will indeed reduce the noise on your 3.3v
plane.
> However, instead of surrounding the plane with two gnd planes, I
would
> suggest adding a second pwr/gnd pair to the stackup to maintain
symmetry.
> Make sure you couple the pwr/gnd pairs as closely as possible. I
usually
> use 4 mil cores for pwr/gnd pairs. If you need 6 routing layers, I
would
> probably try to do the following;
>
> 1) G
> 2) S
> 3) S
> 4) +3.3V
> 5) G
> 6) S
> 7) S
> 8) +3.3V
> 9) G
> 10)S
> 11)S
> 12)G
>
> I wouldn't be surprised if someone else has a better idea, which is
why is
> subscribe.
> Matt
>
> -----Original Message-----
> From: Peterson, James F (FL51) [mailto:james.f.peterson@xxxx]
> Sent: Wednesday, June 18, 2003 6:56 AM
> To: si-list@xxxx
> Subject: [SI-LIST] pcb stackup
>
>
> a typical stackup at our company might look like this:
>
> 1) G
> 2) S
> 3) S
> 4) +3.3V
> 5) S
> 6) S
> 7) G
> 8) S
> 9) S
> 10)G
>
> note that we use layer 4 (+3.3V) as a reference plane.
>
> an alternate stackup is now being pushed here that doesn't allow
this. the
> alternative approach says that this puts too much noise in the
+3.3V plane.
> that we should surround the +3.3V plane with ground planes, as
shown below :
> 1) G
> 2) S
> 3) S
> 4) G
> 5) +3.3
> 6) G
> 7) S
> 8) S
> 9) G
> 10)S
> 11)S
> 12)G
>
> Comments?
>
> thanks,
> Jim Peterson
> Honeywell
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