[SI-LIST] Re: pcb stackup

  • From: Matthew Humphreys <humps@xxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Wed, 18 Jun 2003 08:16:16 -0700

Hi,

The proposed stackup will indeed reduce the noise on your 3.3v plane.
However, instead of surrounding the plane with two gnd planes, I would
suggest adding a second pwr/gnd pair to the stackup to maintain symmetry.
Make sure you couple the pwr/gnd pairs as closely as possible.  I usually
use 4 mil cores for pwr/gnd pairs.  If you need 6 routing layers, I would
probably try to do the following;

1) G
2) S
3) S
4) +3.3V
5) G
6) S
7) S
8) +3.3V
9) G
10)S
11)S
12)G

I wouldn't be surprised if someone else has a better idea, which is why is
subscribe.
Matt

-----Original Message-----
From: Peterson, James F (FL51) [mailto:james.f.peterson@xxxxxxxxxxxxx] 
Sent: Wednesday, June 18, 2003 6:56 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] pcb stackup 


a typical stackup at our company might look like this:

1) G
2) S
3) S
4) +3.3V
5) S
6) S
7) G
8) S
9) S
10)G

note that we use layer 4 (+3.3V) as a reference plane.

an alternate stackup is now being pushed here that doesn't allow this. the
alternative approach says that this puts too much noise in the +3.3V plane.
that we should surround the +3.3V plane with ground planes, as shown below :
1) G
2) S
3) S
4) G
5) +3.3
6) G
7) S
8) S
9) G
10)S
11)S
12)G

Comments?

thanks,
Jim Peterson
Honeywell
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