[SI-LIST] Re: pcb stackup
- From: Alan Hilton-Nickel <AHilton@xxxxxxxxxx>
- To: "'james.f.peterson@xxxxxxxxxxxxx'" <james.f.peterson@xxxxxxxxxxxxx>,jonpowell@xxxxxxxxxxxx, humps@xxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Wed, 18 Jun 2003 12:25:59 -0700
James,
If all your parts are powered from the 3.3V supply, there should be little
or no problem using it as a reference. When you have multiple supplies and
segment your plane to distribute the current, you then have the likely
scenatio of signals crossing plane splits, a certain source of EMI and SI
problems. Pairing the supply with a ground plane allows return currents to
follow the signal trace, minimizing impedance discontinuities.
That said, the less distance between power and ground planes increases the
inter-plane capacitance, which can provide improved decoupling for your
higher speed parts.
Jon's and Mike's observations about ground on the outer planes is correct,
too. You will end up with a lot of plane splits/slots on those outer layers
with the resulting impedance discontinuities on the layers using that outer
layer as a reference. Depending on your needs, you should probably use the
outer layers as breakout and routing or just breakout, and put a plane
directly below for impedance control.
Perhaps this might work better for you:
1) S1
2) GND
3) S2
4) S3
5) 3.3
6) GND
7) S4
8) S5
9) GND
10) S6
Keep in mind that signals on the outer layers will have faster propogation
delays.
Disclaimer: Whether this is a good structure is going to depend a LOT on
your edge rates and timing requirements, which you have not given. If your
signals are switching under 100 psecs and you require length matching on the
order of ~20 psecs (discussion of over-specifying timing requirements I
leave for another thread) then you will likely require more planes.
Something really bleeding edge that still gives you 6 routing layers could
look like this:
1) Breakout
2) GND
3) S1
4) GND
5) 3.3V
6) S2
7) GND
8) S3
9) GND
10) 3.3
11) S4
12) GND
13) S5
14) GND
15) 3.3V
16) S6
17) G
18) Breakout
While this may be extreme, it may be instructive in terms of understanding
what can be done for your boards.
Good luck,
Alan Hilton-Nickel
nVidia Corporation
Santa Clara, CA
> -----Original Message-----
> From: james.f.peterson@xxxxxxxxxxxxx
> [mailto:james.f.peterson@xxxxxxxxxxxxx]
> Sent: Wednesday, June 18, 2003 9:51 AM
> To: jonpowell@xxxxxxxxxxxx; humps@xxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: pcb stackup
>
>
> not a bad question at all.
> it's a good point....we usually move everything down one
> layer to allow for that.
>
> my primary question to all is : do we really have to surround
> our +3.3V planes with gnds? is there an emi concern with
> using the +3.3v plane as a reference plane?
>
> thanks again,
> Jim
>
> -----Original Message-----
> From: Jon Powell [mailto:jonpowell@xxxxxxxxxxxx]
> Sent: Wednesday, June 18, 2003 11:59 AM
> To: humps@xxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: pcb stackup
>
>
> My (perhaps ignorant) question of the week.
>
> If your top and bottom layers are GND (and presumably meant
> as a return signal or reference plane), how do you attach any
> kind of complex IC's without perforating the plane to uselessness?
>
> jon
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Matthew Humphreys
> Sent: Wednesday, June 18, 2003 8:16 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: pcb stackup
>
>
> Hi,
>
> The proposed stackup will indeed reduce the noise on your
> 3.3v plane. However, instead of surrounding the plane with
> two gnd planes, I would suggest adding a second pwr/gnd pair
> to the stackup to maintain symmetry. Make sure you couple the
> pwr/gnd pairs as closely as possible. I usually use 4 mil
> cores for pwr/gnd pairs. If you need 6 routing layers, I
> would probably try to do the following;
>
> 1) G
> 2) S
> 3) S
> 4) +3.3V
> 5) G
> 6) S
> 7) S
> 8) +3.3V
> 9) G
> 10)S
> 11)S
> 12)G
>
> I wouldn't be surprised if someone else has a better idea,
> which is why is subscribe. Matt
>
> -----Original Message-----
> From: Peterson, James F (FL51) [mailto:james.f.peterson@xxxxxxxxxxxxx]
> Sent: Wednesday, June 18, 2003 6:56 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] pcb stackup
>
>
> a typical stackup at our company might look like this:
>
> 1) G
> 2) S
> 3) S
> 4) +3.3V
> 5) S
> 6) S
> 7) G
> 8) S
> 9) S
> 10)G
>
> note that we use layer 4 (+3.3V) as a reference plane.
>
> an alternate stackup is now being pushed here that doesn't
> allow this. the alternative approach says that this puts too
> much noise in the +3.3V plane. that we should surround the
> +3.3V plane with ground planes, as shown below :
> 1) G
> 2) S
> 3) S
> 4) G
> 5) +3.3
> 6) G
> 7) S
> 8) S
> 9) G
> 10)S
> 11)S
> 12)G
>
> Comments?
>
> thanks,
> Jim Peterson
> Honeywell
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