[SI-LIST] Re: pcb stackup
- From: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
- To: adsurevv@xxxxxxxxx, si-list@xxxxxxxxxxxxx,"Doug Brooks" <doug@xxxxxxxxxx>
- Date: Fri, 20 Jun 2003 18:40:16 -0700
Sometimes it is possible to fill unused space in the signal layers to
create plane capacitance. This works if you stack the PCB:
S
P
S
S
P
S
Lee
Lee Ritchey
leeritchey@xxxxxxxxxxxxx
Why Wait? Move to EarthLink.
> [Original Message]
> From: Doug Brooks <doug@xxxxxxxxxx>
> To: <si-list@xxxxxxxxxxxxx>; <adsurevv@xxxxxxxxx>
> Date: 6/20/2003 9:36:06 AM
> Subject: [SI-LIST] Re: pcb stackup
>
> Bingo, it's tough to meet these requirements economically on a 6-layer
board!
>
> Doug
>
>
>
>
> At 01:28 PM 6/19/2003 -0700, Virendra wrote:
> >Doug, how would you propose to get good planer
> >capacitance in a 6 layer board, i have a constraint of
> >overall thickness of 0.062 inches.
> >thanks in advance,
> >
> >virendra
> >
> >--- Doug Brooks <doug@xxxxxxxxxx> wrote:
> > > I also second Matt.
> > >
> > > A good stackup (from a signal integrity standpoint)
> > > meets BOTH of these
> > > conditions:
> > >
> > > 1. Every trace layer is referenced to a plane
> > > 2. There is at least one power/ground plane pair
> > > (per power supply)
> > > (closely coupled, providing good planar capacitance
> > > between)
> > >
> > > (Rick Hartley wrote a good article about this in the
> > > July, 2000, issue of
> > > Printed Circuit Design)
> > >
> > > You need point one for:
> > > loop area control (EMI)
> > > crosstalk control
> > > impedance control
> > >
> > > You need point two for:
> > > high speed decoupling
> > > common mode control (EMI)
> > >
> > >
> > > Pardon the adv, but I have a new book out that
> > > covers all these points
> > > ISBN 0-13-141884-X
> > >
> > > Doug Brooks
> > >
> > >
> > >
> > >
> > > At 09:56 AM 6/18/2003 -0400, you wrote:
> > > >a typical stackup at our company might look like
> > > this:
> > > >
> > > >1) G
> > > >2) S
> > > >3) S
> > > >4) +3.3V
> > > >5) S
> > > >6) S
> > > >7) G
> > > >8) S
> > > >9) S
> > > >10)G
> > > >
> > > >note that we use layer 4 (+3.3V) as a reference
> > > plane.
> > > >
> > > >an alternate stackup is now being pushed here that
> > > doesn't allow this.
> > > >the alternative approach says that this puts too
> > > much noise in the +3.3V
> > > >plane.
> > > >that we should surround the +3.3V plane with ground
> > > planes, as shown below :
> > > >1) G
> > > >2) S
> > > >3) S
> > > >4) G
> > > >5) +3.3
> > > >6) G
> > > >7) S
> > > >8) S
> > > >9) G
> > > >10)S
> > > >11)S
> > > >12)G
> > > >
> > > >Comments?
> > > >
> > > >thanks,
> > > >Jim Peterson
> > > >Honeywell
> > >
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