[SI-LIST] Re: Xilinx decoupling
- From: Mark Alexander <mark.alexander@xxxxxxxxxx>
- To: Martin Euredjian <martin@xxxxxxxxxxxxxx>
- Date: Mon, 16 Dec 2002 12:11:03 -0700
Martin,
I think there's an implicit assumption here that HF capacitors must be mounted
within the FPGA footprint. This is not the case. Yes, in many cases the
optimal position for these capacitors is within the FPGA footprint, as you have
layed them out. Provided you've got continuous power planes in the vicinity of
the device (swiss cheesing with vias at 13 mil dia is permissible), it's fine if
your HF capacitors are around the periphery of the device -- they don't have to
be within the FPGA footprint.
>Of
>course, I'm going on the assumption (rule?) that you don't want your HF caps
>centimeters away from these pins, but as close as possible
That's right. If "as close as possible" is two centimeters from the power pins
of concern, that's fine. With the 0402 capacitors you've got within the FPGA
footprint, it's OK to have the rest of the 0402 capacitors at the outer edge of
their placement radius (in rows around the device).
> ~ 1-2mm trace
>max.
1-2mm is excessive. If possible, draw your capacitor lands with the via
directly against the pad (not trace) and cover the via with solder mask (to
prevent wicking into the via). If this is not available, place the via the
minimum acceptable distance from the land.
Don't get too concerned about the association of "this cap with this power
pin." Within a given supply, all capacitors are associated with all FPGA power
pins. There should be a 1:1 association as far as the quantity of capacitors,
but beyond that, electrically there is not really any specific association of a
particular capacitor to a particular power pin.
Regards,
Mark Alexander
Martin Euredjian wrote:
> Mark,
>
> > What is it about a 1mm pitch device that prevents you from
> > putting enough capacitors on the board?
>
> Where I see a problem is in the inner corner of a package. I'm not doing
> the final layout myself, however, I am trying to specify an attainable
> number of caps in the schematic. I'm doing a rough layout in order to get
> at such things as pin assignments (fanout dependant) and the number and type
> of decoupling caps for some of these large pin count devices.
>
> I'm probably missing something very fundamental, so I'd appreciate any and
> all input on this matter. I'm looking at the FG456 package. Each of the
> inner corners have 4x VCCAUX balls and 4x VCCO balls. Outside these
> corners, you can cover most of the VCCO with 0402's between the VCCO via and
> the corresponding GND via. However, once you get to the inner corners, you
> run out of space. How do you place 8 caps where you can barely fit one. Of
> course, I'm going on the assumption (rule?) that you don't want your HF caps
> centimeters away from these pins, but as close as possible ~ 1-2mm trace
> max.
>
> I've attached a JPEG image depicting the above. It won't make it onto the
> list but it should arrive at your off-list email address.
>
> Thanks,
>
> ===============================
> Martin Euredjian
> eCinema Systems, Inc.
> voice: 661-305-9320
> fax: 661-775-4876
> martin@xxxxxxxxxxxxxx
> www.ecinemasys.com
> ===============================
>
> --------------------------------------------------
> Name: Decoupling copy.jpg
> Decoupling copy.jpg Type: JPEG Image (image/jpeg)
> Encoding: base64
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