[SI-LIST] Re: Xilinx decoupling
- From: Mark Alexander <mark.alexander@xxxxxxxxxx>
- To: martin@xxxxxxxxxxxxxx
- Date: Mon, 16 Dec 2002 10:27:52 -0700
Martin,
You're absolutely right about decoupling of these large devices -- it's
difficult, and there are innumerable tradeoffs involved. However I'm not sure I
agree with one of your statements below:
>With 1mm (or less)
>BGA pitch devices it is physically impossible to reach the "capacitor per
>pin" recommendation we were all programmed with in school.
What is it about a 1mm pitch device that prevents you from putting enough
capacitors on the board? Of the FPGA PCBs that I've evaluated (both those made
for our own internal testing and those of our customers), many of them do
maintain the 1:1 ratio of capacitors to power pins. And guess what -- of the
ones that don't, most of them run into a power supply related problem (excessive
voltage ripple leading to jitter on clocks and other fabric resources).
I'll be very interested to see the feelings of people in this list with regard
to the outrageous numbers of capacitors we're recommending designers use with
our large devices.
Incidentally, we are not seeing a lot of use of 0201 capacitors right now -- it
seems no one wants to manufacture boards with devices this small.
Regards,
Mark Alexander
Martin Euredjian wrote:
> Yet another question on decoupling...
>
> The "capacitor per power pin" recommendation can be found in datasheets
> across the globe. This, coupled to the "number of simultaneous switching
> outputs" metric can result in some pretty hilarious BOM's. The tip of the
> iceberg are application notes that are just plain wrong ... I ran across one
> where you can plug any number into the rise-time portion of the equations
> and still get the same number and size of caps as the output.
>
> On the other hand, there's the practicality of placing N number of caps
> close enough to the device in question. Tantalums are not a problem; as
> long as they are within a couple of cm from the device everything is fine.
> Now, with small-valued chip caps the issue is different. With 1mm (or less)
> BGA pitch devices it is physically impossible to reach the "capacitor per
> pin" recommendation we were all programmed with in school. Even if you use
> tiny 0201 sized devices, it is impossible to cover every power pin unless
> you are willing to give-up something. For example, not using some of the I/O
> pins could eliminate vias --or turn them to GND connections-- which would
> open-up room for on the back side.
>
> I've looked at boards that only have but a handful, maybe eight or so, caps
> under the device and only one tantalum instead of the eight or so you might
> need if you follow data sheets/app notes. I haven't seen many with 0201
> parts yet, although I'm pretty sure they are out there.
>
> The question, then, is:
> What is the practical real-world execution of decoupling such devices?
>
> Thanks,
>
> ===============================
> Martin Euredjian
> eCinema Systems, Inc.
> voice: 661-305-9320
> fax: 661-775-4876
> martin@xxxxxxxxxxxxxx
> www.ecinemasys.com
> ===============================
>
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