[SI-LIST] Xilinx decoupling
- From: "Martin Euredjian" <martin@xxxxxxxxxxxxxx>
- To: "si-list" <si-list@xxxxxxxxxxxxx>
- Date: Mon, 16 Dec 2002 09:21:45 -0800
Yet another question on decoupling...
The "capacitor per power pin" recommendation can be found in datasheets
across the globe. This, coupled to the "number of simultaneous switching
outputs" metric can result in some pretty hilarious BOM's. The tip of the
iceberg are application notes that are just plain wrong ... I ran across one
where you can plug any number into the rise-time portion of the equations
and still get the same number and size of caps as the output.
On the other hand, there's the practicality of placing N number of caps
close enough to the device in question. Tantalums are not a problem; as
long as they are within a couple of cm from the device everything is fine.
Now, with small-valued chip caps the issue is different. With 1mm (or less)
BGA pitch devices it is physically impossible to reach the "capacitor per
pin" recommendation we were all programmed with in school. Even if you use
tiny 0201 sized devices, it is impossible to cover every power pin unless
you are willing to give-up something. For example, not using some of the I/O
pins could eliminate vias --or turn them to GND connections-- which would
open-up room for on the back side.
I've looked at boards that only have but a handful, maybe eight or so, caps
under the device and only one tantalum instead of the eight or so you might
need if you follow data sheets/app notes. I haven't seen many with 0201
parts yet, although I'm pretty sure they are out there.
The question, then, is:
What is the practical real-world execution of decoupling such devices?
Thanks,
===============================
Martin Euredjian
eCinema Systems, Inc.
voice: 661-305-9320
fax: 661-775-4876
martin@xxxxxxxxxxxxxx
www.ecinemasys.com
===============================
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