[SI-LIST] Re: Xilinx decoupling
- From: "Martin Euredjian" <martin@xxxxxxxxxxxxxx>
- To: <mark.alexander@xxxxxxxxxx>
- Date: Mon, 16 Dec 2002 10:46:14 -0800
Mark,
> What is it about a 1mm pitch device that prevents you from
> putting enough capacitors on the board?
Where I see a problem is in the inner corner of a package. I'm not doing
the final layout myself, however, I am trying to specify an attainable
number of caps in the schematic. I'm doing a rough layout in order to get
at such things as pin assignments (fanout dependant) and the number and type
of decoupling caps for some of these large pin count devices.
I'm probably missing something very fundamental, so I'd appreciate any and
all input on this matter. I'm looking at the FG456 package. Each of the
inner corners have 4x VCCAUX balls and 4x VCCO balls. Outside these
corners, you can cover most of the VCCO with 0402's between the VCCO via and
the corresponding GND via. However, once you get to the inner corners, you
run out of space. How do you place 8 caps where you can barely fit one. Of
course, I'm going on the assumption (rule?) that you don't want your HF caps
centimeters away from these pins, but as close as possible ~ 1-2mm trace
max.
I've attached a JPEG image depicting the above. It won't make it onto the
list but it should arrive at your off-list email address.
Thanks,
===============================
Martin Euredjian
eCinema Systems, Inc.
voice: 661-305-9320
fax: 661-775-4876
martin@xxxxxxxxxxxxxx
www.ecinemasys.com
===============================
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