[SI-LIST] Re: Which layer is better for GHz signals
- From: Dan Bostan <dbostan@xxxxxxxxx>
- To: Mike Greim <mike.greim@xxxxxxxxxxx>, Ravinder.Ajmani@xxxxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Thu, 4 Aug 2005 10:06:06 -0700 (PDT)
Assuming the question was about Gbit Ethernet signals,
for 2 in traces, the number of vias (under a
reasonable number-2-3) is not an issue, as long as the
same number of vias are on both members of the diff.
pair.
/dan
--- Mike Greim <mike.greim@xxxxxxxxxxx> wrote:
> Playing devil's advocate, one might
> make the case for routing on outers
> as one can avoid the parasitics associated
> with via stubs or may be able to
> avoid vias altogether.
>
> Seulement mes deux centimes....
>
> Best Regards,
>
> Michael Greim
> Platform Engineering
> Newisys, Inc.
> 512-340-9050, ext 232 (V)
> 512-740-9097 (C)
>
> We will either find a way or make one -Hannibal
>
> And all this science they don't understand
> is just my job six days a week........
>
> The time is gone, the email's over
> Thought I'd something more to say.......
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of
> Dan Bostan
> Sent: Thursday, August 04, 2005 11:33 AM
> To: Ravinder.Ajmani@xxxxxxxxxxxxxx;
> si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Which layer is better for GHz
> signals
>
>
> In general, it is better to use inner layers for
> high
> speed signals, for EMI reasons.
> However, since the GHz traces are differential, the
> radiated field is not as strong as in the case of
> single ended traces.
> From my experience, EMI was not a factor in routing
> such signals.
> Which means, that your other concerns should dictate
> the layer.
> My two cents.
> /dan
>
>
>
> --- Ravinder.Ajmani@xxxxxxxxxxxxxx wrote:
>
> > Hi All,
> > For my next design I am considering a different
> > approach to route the GHz
> > signals. I would like to know the views of other
> > esteemed SI experts on
> > the following two approaches.
> >
> > A) Current Design: Differential traces are routed
> on
> > Top and Bottom
> > layers. The advantage of this approach is that I
> > can route one pair
> > without using any vias, and I get more usable
> board
> > space. The
> > disadvantage is that traces on Top and Bottom
> layers
> > have greater
> > impedance discontinuities due to uneven plating
> and
> > soldermask
> > application.
> >
> > B) Proposed Design: Differential traces will be
> > routed on the inner
> > layers. The advantage here is that the trace
> > impedance will be more
> > uniform as the trace will be covered with
> dielectric
> > on both sides, and
> > there will be no plating. The disadvantage is
> that
> > I will have to use
> > two vias on each trace, and I will have less
> routing
> > space.
> >
> > The reason for considering the new approach is
> > because of the EMI issues
> > with the previous design traced to common-mode
> > currents. I am not sure
> > which design will have less common-mode effect, as
> > one design has
> > discontinuities due to plating/soldermask whereas
> > the other design has
> > discontinuities due to extra vias.
> >
> > The trace length is about 2 inches.
> >
> > Regards, Ravinder
> > Server PCB Development
> > Hitachi Global Storage Technologies
> >
> > Email: Ravinder.Ajmani@xxxxxxxxxxxxxx
> >
> >
>
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