[SI-LIST] Re: Which layer is better for GHz signals
- From: "Mike Greim" <mike.greim@xxxxxxxxxxx>
- To: <dbostan@xxxxxxxxx>, <Ravinder.Ajmani@xxxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 4 Aug 2005 11:53:19 -0500
Playing devil's advocate, one might
make the case for routing on outers=20
as one can avoid the parasitics associated
with via stubs or may be able to=20
avoid vias altogether.
Seulement mes deux centimes....
Best Regards,
Michael Greim
Platform Engineering
Newisys, Inc.
512-340-9050, ext 232 (V)
512-740-9097 (C)
We will either find a way or make one -Hannibal
And all this science they don't understand
is just my job six days a week........
The time is gone, the email's over
Thought I'd something more to say.......
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Dan Bostan
Sent: Thursday, August 04, 2005 11:33 AM
To: Ravinder.Ajmani@xxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Which layer is better for GHz signals
In general, it is better to use inner layers for high
speed signals, for EMI reasons.
However, since the GHz traces are differential, the
radiated field is not as strong as in the case of
single ended traces.
From my experience, EMI was not a factor in routing
such signals.
Which means, that your other concerns should dictate
the layer.
My two cents.
/dan
--- Ravinder.Ajmani@xxxxxxxxxxxxxx wrote:
> Hi All,
> For my next design I am considering a different
> approach to route the GHz=20
> signals. I would like to know the views of other
> esteemed SI experts on=20
> the following two approaches.
>=20
> A) Current Design: Differential traces are routed on
> Top and Bottom=20
> layers. The advantage of this approach is that I
> can route one pair=20
> without using any vias, and I get more usable board
> space. The=20
> disadvantage is that traces on Top and Bottom layers
> have greater=20
> impedance discontinuities due to uneven plating and
> soldermask=20
> application.=20
>=20
> B) Proposed Design: Differential traces will be
> routed on the inner=20
> layers. The advantage here is that the trace
> impedance will be more=20
> uniform as the trace will be covered with dielectric
> on both sides, and=20
> there will be no plating. The disadvantage is that=20
> I will have to use=20
> two vias on each trace, and I will have less routing
> space.
>=20
> The reason for considering the new approach is
> because of the EMI issues=20
> with the previous design traced to common-mode
> currents. I am not sure=20
> which design will have less common-mode effect, as
> one design has=20
> discontinuities due to plating/soldermask whereas
> the other design has=20
> discontinuities due to extra vias.=20
>=20
> The trace length is about 2 inches.
>=20
> Regards, Ravinder
> Server PCB Development
> Hitachi Global Storage Technologies
>=20
> Email: Ravinder.Ajmani@xxxxxxxxxxxxxx
>=20
>
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