[SI-LIST] Re: Which layer is better for GHz signals
- From: "Chris Cheng" <Chris.Cheng@xxxxxxxxxxxx>
- To: "Dan Bostan" <dbostan@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 4 Aug 2005 12:16:12 -0700
Last time I checked, 1G and 2G FCAL disk are all 150ohm differential.
I worked in a storage company, does that answer your question.
-----Original Message-----
From: Dan Bostan [mailto:dbostan@xxxxxxxxx]
Sent: Thursday, August 04, 2005 11:36 AM
To: Chris Cheng; scott@xxxxxxxxxxxxx; michael.mirmak@xxxxxxxxx
Cc: Ravinder.Ajmani@xxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: Which layer is better for GHz signals
How many times you need to route a 150 diff. pair?
This impedance is very unusual.
You have a point with EMI and the return current.
/dan
--- Chris Cheng <Chris.Cheng@xxxxxxxxxxxx> wrote:
> There are practical reasons why microstrip is
> preferred. Try to route 150ohm differential traces
> in a lot of stripline layers and maintaining a thin
> PCB and you will know what I mean.
> I never have problem with EMI with clocks, diff or
> single ended pairs on microstrip. Like I said many
> times, maintaining your current return is the key.
> ________________________________
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> From: si-list-bounce@xxxxxxxxxxxxx on behalf of
> Scott McMorrow
> Sent: Thu 8/4/2005 10:38 AM
> To: michael.mirmak@xxxxxxxxx
> Cc: dbostan@xxxxxxxxx;
> Ravinder.Ajmani@xxxxxxxxxxxxxx;
> si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Which layer is better for GHz
> signals
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> Michael
> Even with minimal differential trace coupling, the
> radiated fields from
> the two sides of a differential pair will cancel
> each other in the far
> field. Generally, it is the common mode components
> of differential
> signals that cause significant radiation.
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> regards,
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> scott
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> Scott McMorrow
> Teraspeed Consulting Group LLC
> 121 North River Drive
> Narragansett, RI 02882
> (401) 284-1827 Business
> (401) 284-1840 Fax
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> http://www.teraspeed.com
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> Teraspeed=AE is the registered service mark of
> Teraspeed Consulting Group LLC
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> Mirmak, Michael wrote:
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> >Dan,
> >
> >Isn't the amount of EMI reduction from the use of
> "differential" traces
> >dependent on the amount of coupling between them?=20
> From the PC-based
> >designs I have seen recently, the coupling between
> microstrip traces is
> >very weak compared to the coupling to the reference
> plane. The traces
> >are more-or-less single-ended in this kind of case,
> with all the EMI
> >radiation effects this implies.
> >
> >Are the traces you have seen very strongly coupled?
> >
> >- Michael Mirmak
> > Intel Corp.
> > Chair, EIA IBIS Open Forum
> >
> >-----Original Message-----
> >From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]
> >On Behalf Of Dan Bostan
> >Sent: Thursday, August 04, 2005 9:33 AM
> >To: Ravinder.Ajmani@xxxxxxxxxxxxxx;
> si-list@xxxxxxxxxxxxx
> >Subject: [SI-LIST] Re: Which layer is better for
> GHz signals
> >
> >In general, it is better to use inner layers for
> high speed signals, for
> >EMI reasons. However, since the GHz traces are
> differential, the
> >radiated field is not as strong as in the case of
> single ended traces.
> >>From my experience, EMI was not a factor in
> routing such signals. Which
> >means, that your other concerns should dictate the
> layer.
> >My two cents.
> >/dan
> >
> >
> >
> >--- Ravinder.Ajmani@xxxxxxxxxxxxxx wrote:
> >
> >=20
> >
> >>Hi All,
> >>For my next design I am considering a different
> >>approach to route the GHz=3D20
> >>signals. I would like to know the views of other
> >>esteemed SI experts on=3D20
> >>the following two approaches.
> >>=3D20
> >>A) Current Design: Differential traces are routed
> on
> >>Top and Bottom=3D20
> >>layers. The advantage of this approach is that I
> >>can route one pair=3D20
> >>without using any vias, and I get more usable
> board
> >>space. The=3D20
> >>disadvantage is that traces on Top and Bottom
> layers
> >>have greater=3D20
> >>impedance discontinuities due to uneven plating
> and
> >>soldermask=3D20
> >>application.=3D20
> >>=3D20
> >>B) Proposed Design: Differential traces will be
> >>routed on the inner=3D20
> >>layers. The advantage here is that the trace
> >>impedance will be more=3D20
> >>uniform as the trace will be covered with
> dielectric
> >>on both sides, and=3D20
> >>there will be no plating. The disadvantage is
> that=3D20
> >>I will have to use=3D20
> >>two vias on each trace, and I will have less
> routing
> >>space.
> >>=3D20
> >>The reason for considering the new approach is
> >>because of the EMI issues=3D20
> >>with the previous design traced to common-mode
> >>currents. I am not sure=3D20
> >>which design will have less common-mode effect, as
> >>one design has=3D20
> >>discontinuities due to plating/soldermask whereas
> >>the other design has=3D20
> >>discontinuities due to extra vias.=3D20
> >>=3D20
> >>The trace length is about 2 inches.
> >>=3D20
> >>Regards, Ravinder
> >>Server PCB Development
> >>Hitachi Global Storage Technologies
> >>=3D20
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>
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