Samsung Enterprise Portal mySingle
P { MARGIN-BOTTOM: 5px; FONT-SIZE: 9pt; FONT-FAMILY: Arial, arial;
MARGIN-TOP: 5px } TD { MARGIN-BOTTOM: 5px; FONT-SIZE: 9pt; FONT-FAMILY:
Arial, arial; MARGIN-TOP: 5px } LI { MARGIN-BOTTOM: 5px; FONT-SIZE: 9pt;
FONT-FAMILY: Arial, arial; MARGIN-TOP: 5px } BODY { FONT-FAMILY: Arial,
arial; MARGIN: 10px; LINE-HEIGHT: 1.4 }
Hi,
Many experts in SI-LIST have been studied this topic deeply. I just share my
humble opinion here.
I had also doubted if a simple 4-element passive model is accurate enough
for PDN Impedance calculation or not.
So I worked on a real VRM design with a hysteretic current model controller.
I set up the average model of this hysteretic-type controller,
and calculated transfer function of VRM close-loop output impedance combined
with output capacitors.
Finally, I found that the calculated transfer function of close-loop output
impedance could be
approximated well by a 4 simple 4-elements R-L circuit and output capacitors
in parallel.
Over few hundred kHz, the zero-poles are mainly contributed by output
capacitors located on PDN or package,
close-loop output impedance of VRM only is so high that can be igorned in
parallel circuit.
Maybe most VRMs can be modeled as a simple 4-elements R-L circuit, even
through a simple 2-elements R-L circuit in AC analysis.
Here is my simple examples,
I wrote it by Octave with signal and control packages,
It shows that LDO can be modeled as a 2-elements R-L circuit,
and a simple voltage model VRM can be modeled as 4-elements or 2-elements
R-L circuit depending on the compensation.
============================================
pkg load control
% LDO Equivalent Output Impedance
% LDO Feedback
R1_LFB = 100e+3;
R2_LFB =175e+3;
alpha_LFB = R1_LFB/(R1_LFB+R2_LFB);
% PMOS
A_PMOS = 1e+2;
rds_PMOS = 100e+3;
% Error Amplifier
A0_LFB = 1e+5;
R_par = 1e+6;
C_par = 3e-12;
% Output Impedance
num_LDO = [rds_PMOS*R_par*C_par, rds_PMOS];
den_LDO = [R_par*C_par, 1+alpha_LFB*A0_LFB*A_PMOS];
sZ_LDO = tf(num_LDO,den_LDO);
% Plot
figure(1);
bode(sZ_LDO);
subplot (2, 1, 1);
title ("Bode Diagram of LDO Output Impedance");
subplot (2, 1, 2);
legend ('Zo',"location", "northeast");
pkg load signal;
% Voltage Mode PWM Equivalent Output Impedance
Vin = 5;
Vramp = 1;
K = Vin/Vramp;
% VM Feedback
R1_VFB = 1e4;
C1_VFB = 470e-12;
R2_VFB = 22e3;
C2_VFB = 1e-9;
% Error Amplifier
A0_VFB = 1e3;
% Inductor
L_VM = 1e-6;
RL_VM = 100e-3;
% Output Impedance
num_VM = conv([L_VM, RL_VM],[R1_VFB*R2_VFB*(A0_VFB+1)*C1_VFB*C2_VFB,
R1_VFB*(C1_VFB+C2_VFB)*(A0_VFB+1)+R2_VFB*C1_VFB, 1]);
den_VM = [R1_VFB*R2_VFB*C1_VFB*C2_VFB*(A0_VFB+1),
R1_VFB*(C1_VFB+C2_VFB)*(A0_VFB+1)+R2_VFB*C1_VFB*(K*A0_VFB+1), K*A0_VFB+1];
sZ_VM = tf(num_VM, den_VM);
% print frequency of zeros and poles
[z,p,k]=tf2zp(sZ_VM);
fz = abs(z)/2/pi
fp = abs(p)/2/pi
% Equivalent Circuit
delta =
(R1_VFB*(C1_VFB+C2_VFB)*(A0_VFB+1)+R2_VFB*C1_VFB)^2
-4*R1_VFB*R2_VFB*(A0_VFB+1)*C1_VFB*C2_VFB;
w_z1 = (R1_VFB*(C1_VFB+C2_VFB)*(A0_VFB+1)+R2_VFB*C1_VFB -
sqrt(delta))/(2*R1_VFB*R2_VFB*(A0_VFB+1)*C1_VFB*C2_VFB);
R_equ_VM = RL_VM/(K*A0_VFB+1);
L_equ_VM = RL_VM/(w_z1*(K*A0_VFB+1));
sZ_equ_VM = tf([L_equ_VM, R_equ_VM],[1]);
printf('Calculated Equivalent Circuit: R = %eohm, L = %eH\r\n', R_equ_VM,
L_equ_VM);
% Plot
figure(2);
bode(sZ_VM,'b',sZ_equ_VM,'r');
subplot (2, 1, 1);
title ("Bode Diagram of PWM Output Impedance");
subplot (2, 1, 2);
legend ('VRM','RL_equ',"location", "southeast");
% If remove C2, it has a more accuracy 4 components Equivalent Circuit
num_VM2 = conv([L_VM, RL_VM],[R1_VFB*C1_VFB*(A0_VFB+1)+R2_VFB*C1_VFB, 1]);
den_VM2 = [R1_VFB*C1_VFB*(A0_VFB+1)+R2_VFB*C1_VFB*(K*A0_VFB+1), K*A0_VFB+1];
sZ_VM2 = tf(num_VM2, den_VM2);
% 4 components Equivalent Circuit
w4_z1 = RL_VM/L_VM;
w4_z2 = 1/(R1_VFB*C1_VFB*(A0_VFB+1)+R2_VFB*C1_VFB);
w4_p1 = (K*A0_VFB+1)/(R1_VFB*C1_VFB*(A0_VFB+1)+R2_VFB*C1_VFB*(K*A0_VFB+1));
R0_equ_VM = RL_VM/(K*A0_VFB+1);
Lout_equ_VM =
L_VM*(R1_VFB*C1_VFB*(A0_VFB+1)+R2_VFB*C1_VFB)/(R1_VFB*C1_VFB*(A0_VFB+1)+R2_VF
B*C1_VFB*(K*A0_VFB+1));
Lslew_equ_VM = R0_equ_VM*((w4_z1+w4_z2-w4_p1)/(w4_z1*w4_z2)-1/w4_p1);
Rflat_equ_VM = w4_p1*Lslew_equ_VM;
printf('4 components Equivalent Circuit: Rflat=%eohm, Lslew=%eH, R0=%eohm,
Lout=%eH\r\n', Rflat_equ_VM, Lslew_equ_VM, R0_equ_VM, Lout_equ_VM);
sZ_equ_VM2 = R0_equ_VM*tf(conv([1/w4_z1,1],[1/w4_z2,1]),[1/w4_p1,1]);
% Plot
figure(3);
bode(sZ_VM2,'b',sZ_equ_VM2,'--r');
subplot (2, 1, 1);
title ("Bode Diagram of PWM Output Impedance w/o C2");
subplot (2, 1, 2);
legend ('VRM w/o C2','4element_equ',"location", "southeast");
============================================
------- Original Message -------
Sender : Istvan Nagy<buenoshun@xxxxxxxxx>
Date : ä¸æ 17, 2016 03:09 (GMT+08:00)
Title : [SI-LIST] Re: VRM bode plot transformation into output imp profile
Hi,
In case one effect (upper FET or lower FET conducting) crates larger Vout
disturbance, then we should just focus on the larger one. In another topic I
mentioned that as a designer I am looking for worst-case conditions. How to
build a model for the larger one, and whether the guys who are supposed to
build it (VRM vendors and their software tools) are actually building such,
I don't know.
I asked few of my assigned FAEs of various VRM vendors on their roadmap
meetings and they didn't know what output impedance was. I have not seen any
vendor tool that actually gives me an output impedance plot either, so there
is the motivation to make the plot myself.
The output impedance profile plot of a VRM has several peaks and valleys, I
don't know how a simple 4-element passive model would be accurate enough.
Maybe a comparison study of output impedance profiles of real VRMs vs their
4-element models would be nice to see.
In decoupling analysis we are looking for two things: one is the main curve
might just have too high impedance for a large section, and narrow impedance
peaks occur at various frequencies. Both should be part of the VRM model.
The impedance profile of the VRM can affect the system impedance profile up
to few hundred kHz.
I just don't like to have too many unknowns in my system.
I don't often find target impedance specs like this, but here is one:
http://www.intel.com/Assets/en_US/PDF/designguide/321736.pdf
page 16 in the pdf.
Basically in most cases there are digital chip (processor, FPGA...) vendors
and there are board/system vendors, they are usually (except for in-house
ASIC) separate companies. I work for a system vendor. The (digital) chip
vendors publish documents with requirements/specs, the system vendors
implement systems complying to those requirements. After this if it still
does not work, then we assume we misunderstood something or the spec is
wrong. For the first case we start debugging together with the chip company
FAE. If that does not lead to a problem resolution then it is case-2. It can
go as far as a lawsuit or mentioning lawsuits, or at least dropping their
chips from our current and next few generation designs. It is nice to try to
understand every bit, but in reality we (system vendors) try to comply to
specs. These specs are almost like legal documents or contracts. I wanted to
model the VRM accurately, so I can tell whether we complied to that spec (of
the CPU/FPGA) or not, even before any prototype was made. Prevention first,
debugging later if needed. Debugging costs a lot more than prevention, can
be $$ millions.
Regards,
Istvan Nagy
-----Original Message-----
From: Smith, Larry
Sent: Friday, January 15, 2016 5:35 PM
To: buenoshun@xxxxxxxxx ; si-list@xxxxxxxxxxxxx ; Istvan Novak
Subject: RE: [SI-LIST] Re: VRM bode plot transformation into output imp
profile
Istvan, Istvan, Steve and all â It depends a lot on what we want to do
with
the VRM models.
If we want to make the VRM stable, check phase margin and gain margin,
optimize output capacitors and check the step response, then we need very
accurate models, probably transistor by transistor. These models would be
appropriate for simulating open loop gain, small-signal impedance and doing
detailed VRM design including selection of the output capacitor.
On the other hand, if we are trying to see how well a PDN meets target
impedance over a broad frequency range, a much simpler VRM model will work.
For power integrity purposes we often want to evaluate on-die capacitance,
package inductance, package capacitors, board power planes, board
capacitors, etc. These considerations are beyond the bandwidth of the VRM
and a complex VRM model just gets in the way.
For one thing, the output of an SMPS (switch mode power supply) VRM is
non-linear and time varying. This is our first hint that a VRM cannot be
modeled very well in the frequency domain. When we check our PDN impedance
against a target impedance, we usually want to use the maximum transient
current (dI) that is likely to be consumed by the load. This often involves
a current step that starts at nearly zero and abruptly rises to nearly the
maximum current that can be delivered by the VRM. We also want to simulate
the opposite step where we start near maximum current and abruptly go to
zero.
VRMs behave very differently for the positive and negative current steps.
For example, the VRM may produce a 50 mV voltage droop on the positive edge
and 100 mV spike on the negative edge. This is very non-linear because we
get twice the voltage for the same delta current depending upon the
direction. This behavior comes from the circuit topology changing in time
(SMPS). A linear VRM can have similar results if there is only a current
pass device and no current pull down device. The output impedance depends
upon the direction of change in large-signal load current. When voltage
waveforms are measured in the time domain, we usually see much more ringing
on the current release compared to the current attack. This indicates the
q-factors are very different. It essentially says that the VRM impedance
cannot be well represented in the frequency domain. VRM large-signal
simulation really only makes sense in the time domain with non-linear
models.
Never-the-less, we need some kind of VRM model in the frequency domain in
order to do our target impedance simulation and evaluate the high frequency
components of the PDN. We certainly do not want to hook an ideal voltage
source (zero output impedance) to our bulk capacitors and our PDN rail.
This was the motivation for simple 2 and 4 element linear models for the
VRM. They are used to connect an ideal voltage source to the rest of the
VRM for target impedance simulations but should never be used to evaluate
the behavior of the VRM. The simple model does not look so bad once we
realize that it is not possible to accurately represent the VRM in the
frequency domain for the target impedance simulation. It gives reasonable
results in both the frequency and time domains.
My friend at work likes to say, âThere are no accurate models but some
models are useful.â That applies to this situation. We need to choose
models for the simulation at hand and be careful to interpret the results
appropriately.
Regards,
Larry Smith
PS - Janine Love has set up at time for us to meet at DesignCon. Perhaps we
can discuss this further at that time. 12:45 PM on Thursday, room M1.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Istvan Nagy
Sent: Thursday, January 14, 2016 8:51 AM
To: si-list@xxxxxxxxxxxxx; Istvan Novak
Subject: [SI-LIST] Re: VRM bode plot transformation into output imp profile
Hi,
Actually I am concerned about both but separately: stability and output
impedance.
Stability for its own sake (it has to be stable), and impedance for
decoupling analysis.
For stability currently we rely on VRM-vendor-FAE and their simulations. For
frequency domain decoupling and impedance profile I have to rely on myself
(designer and SI engineer in one is my role).
For example Intel (used to?) provide a target impedance curve, that is flat
for low freq (VRM and bulk caps region), then from 20MHz it increase the
impedance line by 20db/decade if I remember correctly. To meet a requirement
like that with my system actual impedance profile, all elements (VRM, bulk
caps, cer caps, powerplanes) have to be below the curve. The VRM imp profile
was unknown to me so far, the others were easy to simulate/generate.
I will be on DesignCon on wed/thurs.
Regards,
Istvan Nagy
-----Original Message-----
From: Istvan Novak
Sent: Thursday, January 14, 2016 5:23 AM
To: buenoshun@xxxxxxxxx ; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: VRM bode plot transformation into output imp
profile
Istvan,
As Steve pointed out, the vendor models are first order, giving you
overall guidance about the highest-level bits only.
We had models from popular vendors where even the first-order behavior
was very off. So back to Steve's point, and something I also wanted to
stress again: you need (your own) test results.
You say you are concerned about impedance profile rather than converter
stability. Actually the two go hand-in-hand. If you understand how to
read the results, you can get a reasonably good feel about the shape of
the impedance curve just by looking at the Bode plot (but you wont get
absolute numbers without having additional info). On the other hand, if
you look at the impedance curve, you can have a pretty good idea about
the loop stability. In this sense I agree with you that you dont need
to care for the loop stability: if the impedance profile looks OK, it
automatically means you have enough phase and gain margin.
BTW: dependent on whos components you use, some vendors also provide the
approximate output impedance plot inside the same tool.
If you are at DesignCon next week, we can talk more.
Regards,
Istvan Novak
Oracle
On 1/13/2016 12:14 PM, Istvan Nagy wrote:
Istvan,vendorââ¬â¢s
Thank you. Its good to know all those effects. Even then we start with a
simulation before prototype, and I prefer going as far as possible at this
stage as a starting point.
My point is: I assume the VRM vendors built very accurate averaged or
spice or whatever models (transistor-level, etc) inside their simulation
tools. I cannot get these models from them to use in my chosen simulation
tool, but I can get the bode plot from their tool. Then all i need is
transforming their output (bode plot) into the impedance profile plot.
Then transforming that into an s-parameter (touchstone) file. Then placing
this s-parameter file into my system-PI simulation.
So I am not looking to build/use averaged neither spice models of the VRMs
in my simulations, but want to create the s-parameter model from bode
plot.
I am sure the VRM vendors can build more accurate averaged models for
their chips than I could, so I don't bother building such models anymore.
I am NOT trying to build a functional VRM model. I tried before (like in
my pdf), but now I am abandoning it. Instead I want to extract the o.imp
profile from the vendor's tool.
It might still not be 100% accurate, but it is more accurate than the
model I would build for their chip. I just want to take advantage of this
(the work the vrm vendor did with modelling), and eliminate the
hassle/risk (risk of mistake) of building averaged or spice models myself.
The other thing is, I want to see the complete impedance profile of the
PDN (vrm+bulkcaps+cercaps+pplane+bgapackage) before building the proto.
VRM stability is analyzed in the VRM-vendor's tool, so in this discussion
I am not aiming for that. I want to see whether the PDN impedance profile
meets the target impedance profile (line or curve). Especially at lower
frequencies.
So the VRM should be optimized both for stability (bode) and for
decoupling and target impedance (o.imp.).
"you can apply simple calculations of an amplifier block with a feedback."
-Remind me, what these calculations are exactly? Where can I find the
equations? Because that's what I was looking for.
" 'transparency' that your output impedance also depends on the source
impedance."
I may have to build 2-stage models or worst-case models. My 110V/12V main
PSU then the 12V/0.9V core regulator in series for example.
For the layout effects, I am hoping proper design techniques can reduce
them significantly. Simulating together with layout would be very
difficult to arrange with vrm vendorââ¬â¢s tools and system
boards (my designs). It would probbaly require the system vendor to have
access to VRM spice/averaged/other models directly. With my post I am
trying to eliminate this need and get a good compromise solution.
Faraydon,
That's what I am looking for, but with more detail.
Regards,
Istvan Nagy
From: istvan.novak@xxxxxxxxxxx
Sent: Wednesday, January 13, 2016 5:04 AM
To: buenoshun@xxxxxxxxx ; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] VRM bode plot transformation into output imp
profile
Hi Istvan,
You are not alone with this challenge, but as usual, the answer is "it
depends",
and there is no single generic answer to this question that could fit the
very
wide spectrum of circuits and applications. The first thing to keep in
mind:
as Lee often reminds this list, you get what you pay for.
Going from loop gain to closed-loop output impedance: the theory
is there. You dont even need to pick up one of the many books on DC-DC
converter designs; you can apply simple calculations of an amplifier block
with a feedback. However, you have to set the expectations right: if you
think that your simple averaged model may not capture all of the effects,
you should not think that using the Bode plot predicted by a vendor tool
(which most of them are also averaged, and capture only the first-order
effects) will give you the details you missed in your simple model; it
will not.
The biggest challenge in these days is coming from all of the secondary
effects
that are very hard to model. Many years ago converters tended to be
stand-alone, well-isolated blocks, where source and load conditions had
less influence on the performance. As we tend to reduce those input/output
barriers to achieve cost and size reduction, you will find that many
converters
today will show enough 'transparency' that your output impedance also
depends
on the source impedance. Also, if you DO count on any of the nonlinear
functions of modern controllers, you should not expect to capture it with
a
simple SPICE model. The selection of control-loop type also makes a big
difference: some (like current-mode control) are more friendly to simple
modeling, because they tend to be less sensitive to second-order effects.
Some others, like constant ON time and hysteretic-type controllers have
a tendency to be much more sensitive to things like layout details, which
are much harder to capture in simple models. Sometimes the same exact
circuit, even if you literally move the same components, may perform
very differently dependent on the board stackup and small layout details.
Some of these challenges were described in past publications, for instance
http://www.electrical-integrity.com/Paper_download_files/DC12_11-MP2.pdf
http://www.electrical
(this second paper described second-order scenarios that should be easy
to simulate if you have the proper averaged model for the converter.
At DesignCon 2016 you will also find multiple talks that touch on this
subject
and we can chat if you attend.
We all have the desire to do pre-layout and post-layout simulations to
capture
potential problems before we build our boards. In my experience though,
unless we can afford significant overdesign, you should always allow for
iterations and design changes after your first build, and the changes
should
be based on actual validation. This of course refers to cases when the
performance details matter; but otherwise why would you want to do
more accurate simulations before you build the board?
Regards,
Istvan Novak
Oracle
On 01/13/16, Istvan Nagy wrote:
Hi,
This post is about theories on VRM modelling.
For power integrity analysis ideally we should combine the
frequency-responses of the VRM (output impedance profile), all the
capacitors, the power planes and maybe some properties of the chips (pin
inductance, package decaps..). I would do this combined simulation in AC
small signal mode in SPICE or ADS or similar. The model of the capacitors
is
easily simulated (3-element ESL/ESR/C), the power planes can be extracted
with 2.5D-3D EM simulators into touchstone files. But, the VRM model is
what
I find more problems with. Older publications suggested 2-element or
4-element lumped models that are probably not accurate at all, especially
for modern digital controllers. Building an "averaged model" would not be
possible for me, as I am not working at the VRM-chip companies. I tried to
make estimated models for VRM, but they are probably very inaccurate, as I
cannot model all the effects in the VRM with my simple spice models:
http://www.buenos.extra.hu/download/QUCS_PowerIntegrity-doc.pdf
So, I thought we could get more accurate VRM models for power delivery
system impedance profile simulation by transforming the bode plot into an
impedance profile. I think they basically describe the same thing but in
different ways, closed vs open loop and current vs voltage source being
used. Then impedance/frequency (Z-parameter) plots can be transformed into
S-parameter/frequency plots (touchstone file) in easy and known ways. Then
these touchstone files can be placed as components in AC simulation is
QUCS-spice or Agilent-ADS.
All VRM chip vendors provide simulation tools to generate "OPEN loop GAIN
(bode plot)". So we can get this plot for every project easily. Maybe we
could transform this plot into a "CLOSED loop output IMPEDANCE profile".
Most/any chip vendors don't provide tools to generate the impedance
profile,
I don't know enough about the internals of each VRM to build accurate
models
that I can simulate directly for output impedance, but Bode tools are
common
and easily available.
The problem is, I have no idea how to transform one into the other, and no
idea whether it is possible at all. That's my missing link.
"OPEN loop GAIN (bode plot)" ==[??]==> "CLOSED loop output IMPEDANCE
profile".
What I am looking for is a reusable model, equations or tools, so for
every
rail in every project I could simulate the PI quickly.
Any comments?
Is it possible?
Regards,
Istvan Nagy
Board/hardware design engineer
---
This email has been checked for viruses by Avast antivirus software.
https://www.avast.com/antivirus
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
---
This email has been checked for viruses by Avast antivirus software.
https://www.avast.com/antivirus
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
