Hi,
This post is about theories on VRM modelling.
For power integrity analysis ideally we should combine the
frequency-responses of the VRM (output impedance profile), all the
capacitors, the power planes and maybe some properties of the chips (pin
inductance, package decaps..). I would do this combined simulation in AC
small signal mode in SPICE or ADS or similar. The model of the capacitors is
easily simulated (3-element ESL/ESR/C), the power planes can be extracted
with 2.5D-3D EM simulators into touchstone files. But, the VRM model is what
I find more problems with. Older publications suggested 2-element or
4-element lumped models that are probably not accurate at all, especially
for modern digital controllers. Building an "averaged model" would not be
possible for me, as I am not working at the VRM-chip companies. I tried to
make estimated models for VRM, but they are probably very inaccurate, as I
cannot model all the effects in the VRM with my simple spice models:
http://www.buenos.extra.hu/download/QUCS_PowerIntegrity-doc.pdf
So, I thought we could get more accurate VRM models for power delivery
system impedance profile simulation by transforming the bode plot into an
impedance profile. I think they basically describe the same thing but in
different ways, closed vs open loop and current vs voltage source being
used. Then impedance/frequency (Z-parameter) plots can be transformed into
S-parameter/frequency plots (touchstone file) in easy and known ways. Then
these touchstone files can be placed as components in AC simulation is
QUCS-spice or Agilent-ADS.
All VRM chip vendors provide simulation tools to generate "OPEN loop GAIN
(bode plot)". So we can get this plot for every project easily. Maybe we
could transform this plot into a "CLOSED loop output IMPEDANCE profile".
Most/any chip vendors don't provide tools to generate the impedance profile,
I don't know enough about the internals of each VRM to build accurate models
that I can simulate directly for output impedance, but Bode tools are common
and easily available.
The problem is, I have no idea how to transform one into the other, and no
idea whether it is possible at all. That's my missing link.
"OPEN loop GAIN (bode plot)" ==[??]==> "CLOSED loop output IMPEDANCE
profile".
What I am looking for is a reusable model, equations or tools, so for every
rail in every project I could simulate the PI quickly.
Any comments?
Is it possible?
Regards,
Istvan Nagy
Board/hardware design engineer
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