Hi Istvan,
You are not alone with this challenge, but as usual= , the answer is "it
depends",
and there is no single generic= answer to this question that could fit the
very
wide spectrum of circ= uits and applications. The first thing to keep in
mind:
as Lee o= ften reminds this list, you get what you pay for.
Going from loo= p gain to closed-loop output impedance: the theory
is there. You= dont even need to pick up one of the many books on DC-DC
converter de= signs; you can apply simple calculations of an amplifier block
with a = feedback. However, you have to set the expectations right: if you
think that your simple averaged model may not capture all of the effects,=
you should not think that using the Bode plot predicted by a vendor t= ool
(which most of them are also averaged, and capture only the first-= order
effects) will give you the details you missed in your simple mod= el; it
willnot.
The biggest challenge in these days is coming f= rom all of the secondary
effects
that are very hard to model. Ma= ny years ago converters tended to be
stand-alone, well-isolated blocks= , where source and load conditions had
less influence on the performan= ce. As we tend to reduce those
input/output
barriers to achieve = cost and size reduction, you will find that many
converters
today will= show enough 'transparency' that your output impedance also
depends
on= the source impedance. Also, if you DO count on any of the
nonlinearfunctions of modern controllers, you should not expect to capture
itw= ith a
simple SPICE model. The selection of control-loop type als= o makes a big
difference: some (like current-mode control) are more fr= iendly to simple
modeling, because they tend to be less sensitive to s= econd-order effects.
Some others, like constant ON time and hysteretic= -type controllers have
a tendency to be much more sensitive to things = like layout details, which
are much harder to capture in simple models= . Sometimes the same exact
circuit, even if you literally move t= he same components, may perform
very differently dependent on the boar= d stackup and small layout details.
Some of these challenges wer= e described in past publications, for instance
http://www.electrical-integrity.com/Paper_download_files=
/DC12_11-MP2.pdf[1]
http://www.electrical-integrity.com/Paper_downl=
oad_files/DC15_11_FR1_Paper_ImpactofRegulatorSense_point.pdf[2]
(this= second paper described second-order scenarios that should be easy
to = simulate if you have the proper averaged model for the converter.
At D= esignCon 2016 you will also find multiple talks that touch on this
su=bject
and we can chat if you attend.
We all have the desire= to do pre-layout and post-layout simulations to
capture
potential pro= blems before we build our boards. In my experience though,
unles= s we can afford significant overdesign, you should always allow for
it= erations and design changes after your first build, and the changes
shouldbe based on actual validation. This of course refers to cases wh= en
the
performance details matter; but otherwise why would you want to= do
more accurate simulations before you build the board?
R= egards,
Istvan Novak
Oracle
&nb= sp; On 01/13/16, Istvan Nagy<buenoshun@xxxxxxxxx> wrote:= Hi,
This post is about theories on VRM modelling.
For power integrity analysis ideally we should combine the
fre= quency-responses of the VRM (output impedance profile), all the
capac= itors, the power planes and maybe some properties of the chips (pin
i= nductance, package decaps..). I would do this combined simulation in AC
small signal mode in SPICE or ADS or similar. The model of the capacitor= s
is
easily simulated (3-element ESL/ESR/C), the power planes can be = extracted
with 2.5D-3D EM simulators into touchstone files. But, the = VRM model is
what
I find more problems with. Older publications sugge= sted 2-element or
4-element lumped models that are probably not accur= ate at all, especially
for modern digital controllers. Building an &q= uot;averaged model" would
notbe
possible for me, as I am not wo= rking at the VRM-chip companies. I tried to
make estimated models for= VRM, but they are probably very inaccurate, as I
cannot model all th= e effects in the VRM with my simple spice models:
http://www.buenos.extra.hu/download/QUCS_PowerIntegrity= -doc.pdf[3]
So, I thought we could get more accurate VRM models for p= ower delivery
system impedance profile simulation by transforming the= bode plot into an
impedance profile. I think they basically describe= the same thing but in
different ways, closed vs open loop and curren= t vs voltage source being
used. Then impedance/frequency (Z-parameter= ) plots can be transformed into
S-parameter/frequency plots (touchsto= ne file) in easy and known ways. Then
these touchstone files can be p= laced as components in AC simulation is
QUCS-spice or Agilent-ADS.All VRM chip vendors provide simulation tools to
generate "OPEN loo= p GAIN
(bode plot)". So we can get this plot for every project e= asily. Maybe we
could transform this plot into a "CLOSED loop ou= tput IMPEDANCE profile".
Most/any chip vendors don't provide too= ls to generate the impedance
profile,
I don't know enough about the i= nternals of each VRM to build accurate
models
that I can simulate dir= ectly for output impedance, but Bode tools are
common
and easily avai= lable.
The problem is, I have no idea how to transform one into the ot= her, and no
idea whether it is possible at all. That's my missing lin= k.
"OPEN loop GAIN (bode plot)" =3D=3D[??]=3D=3D> "C= LOSED loop output
IMPEDANCE
profile".
What I am looki= ng for is a reusable model, equations or tools, so for
every
rail in = every project I could simulate the PI quickly.
Any comments?
Is i= t possible?
Regards,
Istvan Nagy
Board/hardware design= engineer
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