[SI-LIST] Re: Reaching 2 Gbps out of a single-ended interface
- From: "Michael J. Degerstrom" <degers@xxxxxxxxxxxxxxxxxxxx>
- To: strembl1@xxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Thu, 24 Oct 2002 08:53:31 -0500
Stephane,
60 ohm impedance on FR-4 is tough to do without the crosstalk canceling
the benefits from the higher impedance.
I agree that dI/dt noise on your package is most likely to be your biggest
challenge. Basically your signal to ground ratio has to be low (lots of
ground pins/bond-wires). Don't lump the grounds together but spread them out
for lowest inductance. I'm not sure if you intend to terminate on the
receiver chip or on the board. If the former then you'll have switching
noise on VDD at the receiver side. If the latter then your path from the
termination to the receiver will behave like a stub.
I typically tackle these kind of problems by taking a slice of I/O with
powers/grounds included. This model will include output buffers,
power/ground package inductance, coupled pcb wiring, and receiver package and
buffer models. Then I drive each output driver with independent random bit
streams and plot the resulting eye diagrams. Its more of a 'big picture'
look which may mask contributions from various sources. So it may be
instructive to simplify the model to see what your major contributors are
that degrade your signal quality. Remember, that everything may look fine
at certain pcb lengths but things may fall apart at the resonance conditions.
To check this repeat the analysis at various line lengths. You may have to
restrict lines of certain lengths.
Mike
--
Mike Degerstrom email: degers@xxxxxxxxxxxxxxxxxxxx
Advanced Signal Integrity Design, LLC http://www.advancedsidesign.com
On Wednesday 23 October 2002 04:00 pm, Stephane Tremblay wrote:
> Hi SI-Listers,
>
> I have an interesting challenge to accomplish: bring a 70 bits
> single= ended interface in the 2 Gbps range (1 GHz clock, DDR xfers). Here
> is how I= plan on doing it:
>
> Rails
> - VDD =3D 1.8 V
> - VSS =3D 0V
>
> Output buffer
> - Impedance: 40 Ohms Pull-UP
> 40 Ohms Pull-Down (so the '0' is at about 0.72 V)
> (I prefer overshoot better than undershoot considering the 60 Ohms
> T-line= and receiver)
> - Slew-Rate: 9V/ns
> - Parasitic capacitance (including ESD): < 4 pF
> - Assume very linear VI curves
> - Assume a 50% duty-cycle with matched falling and rising edges
> - Assume a 30 ps jitter on output.
>
> Input buffer
> - Termination Impedance: 60 Ohms to VDD
> - Assume very linear VI curve for termination
> - Vref @ 1.26V =20
> - Parasitic capacitance (including ESD): < 4 pF
>
> Interconnect (flip-chip package and FR4 pcb)
> - 4 inches symmetric Stripline 60 Ohms on FR4
> - Package Impedance discontinuity on signal: 200 mOhms, 1.5nH, 0.3pF
>
>
> By putting aside the crosstalk consideration, I really think the signal=
> quality can be OK with this basic model. One of the biggest concern that
> I= have is Rail collapse. If I put the numbers:
>
> dI/dt =3D 70 bits x 9 V/ns / 60 Ohms =3D 10.5 A/ns
>
> Considering a maximum allowable swing of 75 mV on rails,=20
>
> I get max allowable GND/PWR inductance of 7 pH. Note that GND is more=
> important since the receiver terminate the line at VDD.
>
> Now the questions:
>
> 1- Is there any hole with my assumptions?
> 2- Should I worry about other factors than Rail collapse (crosstalk and
> EMI= excluded)
> 3- Is 7 pH of total GND inductance do-able?
> 4- What would you specify differently if you were me? And why?
> 5- Is anyone ever pushed a 70 bits single ended interface that fast? How?
>
> Thanks for the answers,
> Steph.
>
> ______________________________________________
>
> St=E9phane Tremblay
> Hardware project leader
>
> Matrox Graphics Inc. (MGI)=20
> 1025 St-Regis, Dorval (Quebec), H9P 2T4=20
>
> Telephone : (514) 822-6300 #2930=20
> Fax : (514) 685-7030=20
> email : Stephane.Tremblay@xxxxxxxxxx=20
> ______________________________________________
> USA address : Matrox Graphics Inc.=20
> 625 State Route 3 #B=20
> Plattsburg, NY, USA, 12901-6530=20
> ______________________________________________
>
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