[SI-LIST] Re: Reaching 2 Gbps out of a single-ended interface
- From: "Jean Audet" <jaudet@xxxxxxxxxx>
- To: strembl1@xxxxxxxxxx
- Date: Thu, 24 Oct 2002 09:11:27 -0400
Dear Stephane, First of all, SSIO noise is not related to gnd-vdd loop
inductance. The Vdd-gnd loop is related to ON CHIP SSN. The Loop for the
output IO is form by the net itselfs and the VDD or GND inductance path
(depending the way it's switch (Low to High or High to Low).
FYI the power distribution of a build up carrier is in general not so good
if you have many IO's to be faned out. I do not know How big is the chip
and how many signal I/O you have to faned out.
The weakness of the build up carrier is the following:
The signal are wired out on the first (1-3) top buildup layers and
depending the chip footprint image, it may be necessary to remove many
pwr/gnd vias to allow the wiring on the next buildup layer. By making that
, the number of powr / gnd vias is affected. As an example for very high IO
count, the numbers of vias (micro and PTH in the chip area are small and
consequently, making DC IR droop (compression of vdd-gnd), and higher
pwr/gnd inductance.
Question: Are you planning to use off chip decap ? If yes what is the loop
inductance from the chip to the decap ?
An other important point in your case is the potential impact of the signal
reflection for those HS nets (1Ghz) and make sure that those
discontinuities meet you requirement. Attention must be taken for PTH
design , micro via and BGA pad. Good design knowledge is required to
ensure the first pass success. The number you gave for the capacitive
discontinuities on the package is not correct ...make sure you have
verified every capacitive discontinuities of the total signal net path.
Also, verify the manufacturing Impedance tolerance from your buildup
supplier....you may have 10-20% tolerance from part to part.
For your board (4 inches lines )...make sure it is well terminated
Jean Audet
Electrical Analysis
InterConnect Products IMD
IBM Burlington
Tel: 802-769-0835, tie line: 446-0835
Tel: 450-534-6317, tie line: 552-6317
E-mail: jaudet@xxxxxxxxxx
Stephane Tremblay
<strembl1@matrox. To: si-list@xxxxxxxxxxxxx
com> cc:
Sent by: Subject: [SI-LIST] Reaching 2
Gbps out of a single-ended interface
si-list-bounce@fr
eelists.org
10/23/2002 05:00
PM
Please respond to
strembl1
Hi SI-Listers,
I have an interesting challenge to accomplish: bring a 70 bits single
=
ended interface in the 2 Gbps range (1 GHz clock, DDR xfers). Here is how
I=
plan on doing it:
Rails
- VDD =3D 1.8 V
- VSS =3D 0V
Output buffer
- Impedance: 40 Ohms Pull-UP
40 Ohms Pull-Down (so the '0' is at about 0.72 V)
(I prefer overshoot better than undershoot considering the 60 Ohms T-line
=
and receiver)
- Slew-Rate: 9V/ns
- Parasitic capacitance (including ESD): < 4 pF
- Assume very linear VI curves
- Assume a 50% duty-cycle with matched falling and rising edges
- Assume a 30 ps jitter on output.
Input buffer
- Termination Impedance: 60 Ohms to VDD
- Assume very linear VI curve for termination
- Vref @ 1.26V =20
- Parasitic capacitance (including ESD): < 4 pF
Interconnect (flip-chip package and FR4 pcb)
- 4 inches symmetric Stripline 60 Ohms on FR4
- Package Impedance discontinuity on signal: 200 mOhms, 1.5nH, 0.3pF
By putting aside the crosstalk consideration, I really think the signal=
quality can be OK with this basic model. One of the biggest concern that I
=
have is Rail collapse. If I put the numbers:
dI/dt =3D 70 bits x 9 V/ns / 60 Ohms =3D 10.5 A/ns
Considering a maximum allowable swing of 75 mV on rails,=20
I get max allowable GND/PWR inductance of 7 pH. Note that GND is more=
important since the receiver terminate the line at VDD.
Now the questions:
1- Is there any hole with my assumptions?
2- Should I worry about other factors than Rail collapse (crosstalk and EMI
=
excluded)
3- Is 7 pH of total GND inductance do-able?
4- What would you specify differently if you were me? And why?
5- Is anyone ever pushed a 70 bits single ended interface that fast? How?
Thanks for the answers,
Steph.
______________________________________________
St=E9phane Tremblay
Hardware project leader
Matrox Graphics Inc. (MGI)=20
1025 St-Regis, Dorval (Quebec), H9P 2T4=20
Telephone : (514) 822-6300 #2930=20
Fax : (514) 685-7030=20
email : Stephane.Tremblay@xxxxxxxxxx=20
______________________________________________
USA address : Matrox Graphics Inc.=20
625 State Route 3 #B=20
Plattsburg, NY, USA, 12901-6530=20
______________________________________________
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