[SI-LIST] Re: pwr-gnd loop inductance measurment
- From: "Jean Audet" <jaudet@xxxxxxxxxx>
- To: chris.cheng@xxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Thu, 24 Oct 2002 09:19:19 -0400
Depending the package you are using, you may have current flowing through
the plane or power strap... This may be the case for some particular design
using the buildup technology. and you are right , on-chip decap are used
but for some application you can not put as many decap as you want and you
may be limited in space....
And in my case I'm interrested to see the impact of a new SLGA interconnect
versus other LGA connector...How good is versus others
Jean Audet
Electrical Analysis
InterConnect Products IMD
IBM Burlington
Tel: 802-769-0835, tie line: 446-0835
Tel: 450-534-6317, tie line: 552-6317
E-mail: jaudet@xxxxxxxxxx
Chris Cheng
<chris.cheng@3par To: si-list@xxxxxxxxxxxxx
data.com> cc:
Sent by: Subject: [SI-LIST] Re: pwr-gnd
loop inductance measurment
si-list-bounce@fr
eelists.org
10/23/2002 03:20
PM
Please respond to
chris.cheng
Ray and friends,
I am always curious in the days of flip chip BGA's how does one view the
pwr/gnd loop inductance of a package ?
Does the core pwr/gnd current really flow through the BGA pwr/gnd planes or
does it really flow straight up from the C4 bump under the die through the
via from the PCB ? Does the presence of power/gnd planes in a BGA is more
to
do with referencing the I/O and for the switching current to return. In the
later case measuring the pwr/gnd loop inductance is meaningless unless the
on die decoupling is presence and a specific I/O loop is known.
In other words, why do we even need to measure the pwr/gnd plane loop
inductance ?
Chris
-----Original Message-----
From: Ray Anderson [mailto:Raymond.Anderson@xxxxxxx]
Sent: Wednesday, October 23, 2002 11:51 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: pwr-gnd loop inductance measurment
>
>I'm trying to correlate pwr-gnd loop Inductance of a bga package
>calculted from S11 and S21 measurement (VNA).
>
>FYI, For extracting the Inductance from S21 measurement ,
>1. I measure the capacitance of the vdd-gnd ,
>2. Short the BGA side (all vdd and gnd ball shorted together)
>3. measurement the s21 on vdd-gnd on the top side (C4 pad).
>4. Based on the first peak (resonance) I calculate the L .
>
>For S11, I think it is little more complicated, because we measure a
>package with a very low impedance versus the 50Ohms cable, and maybe the
>calibration is difficult ? Is someone have experience using S11 for the
the
>pwr-gnd loop inductance of a bga paclkage?.. Also is someone try to find
>this very low loop inductance (a couple pH) with a TDR ?.. If yes, have
you
>seen any chalenges.?
>
>Thanks
The S21 method you describe above is what we typically use in our lab
for measuring package inductance as well as mounting pad/via inductances.
We have achieved good correlation of our lab measurements with HFSS
simulations of the same geometry.
Your comments on the S11 measurements are correct. The calibration is
difficult because it is very difficult to account for the probe inductance.
Also, as you've pointed out, measuring small impedances with a 50
ohm instrument is error prone. S21 measurements have a much larger
dynamic range.
-Ray Anderson
Sun Microsystems
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