[SI-LIST] Re: Reaching 2 Gbps out of a single-ended interface

  • From: "Scott McMorrow" <scott@xxxxxxxxxxxxx>
  • To: strembl1@xxxxxxxxxx
  • Date: Wed, 23 Oct 2002 15:39:07 -0700

Stephane,

There are several additional issues to consider:

1) Resonance:  4 " of interconnect with imperfect termination will have 
a resonant frequency ranging from 250 MHz to 600 MHz, depending on the 
velocity of propagation, and whether a  quarter or half-wave resonant 
mode is excited.  When your data pattern approaches resonant frequency, 
the bit jitter will skyrocket.  There will actually be several resonant 
frequencies due to the uneven nature of the interconnect at the package 
board boundaries and the termination boundary.  A frequency domain sweep 
of the interconnect will tell you much about the resonance behavior.

2) Crosstalk: Modal impedance changes on the interconnect due to 
crosstalk will cause resonance conditions to appear that might not have 
otherwise appeared.  Control of crosstalk will be necessary to reduce 
the dynamic change in impedance and reduce the total mismatch.

3) Signal Return Path:  If the return path for the signals are not 
well-controlled in the packages, you may find additional noise and 
mismatches that were total unexpected.  In order to analyze these, 3-D 
EM software will be required.

4) Pattern dependencies:  Since different data patterns excite different 
frequency harmonics, it will be necessary to simulate the interconnect 
with a broadband pattern that is representative of your data stream.

5) Corners:  You will want to simulate the interconnect across all 
package, PCB and process corners, in order to be sure that you have 
covered all the resonance bases.

best regards,

scott


-- 
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com




Stephane Tremblay wrote:

>Hi SI-Listers,
>
>      I have an interesting challenge to accomplish: bring a 70 bits single=
> ended interface in the 2 Gbps range (1 GHz clock, DDR xfers). Here is how I=
> plan on doing it:
>
>Rails
>      - VDD =3D 1.8 V
>      - VSS =3D 0V
>
>Output buffer
>      - Impedance: 40 Ohms Pull-UP
>                         40 Ohms Pull-Down (so the '0' is at about 0.72 V)
>  (I prefer overshoot better than undershoot considering the 60 Ohms T-line=
> and receiver)
>      - Slew-Rate: 9V/ns
>      - Parasitic capacitance (including ESD): < 4 pF
>      - Assume very linear VI curves
>      - Assume a 50% duty-cycle with matched falling and rising edges
>      - Assume a 30 ps jitter on output.
>
>Input buffer
>      - Termination Impedance: 60 Ohms to VDD
>      - Assume very linear VI curve for termination
>      - Vref @ 1.26V =20
>      - Parasitic capacitance (including ESD): < 4 pF
>
>Interconnect (flip-chip package and FR4 pcb)
>      - 4 inches symmetric Stripline 60 Ohms on FR4
>      - Package Impedance discontinuity on signal: 200 mOhms, 1.5nH, 0.3pF
>
>
>By putting aside the crosstalk consideration, I really think the signal=
> quality can be OK with this basic model. One of the biggest concern that I=
> have is Rail collapse. If I put the numbers:
>
>dI/dt =3D 70 bits x  9 V/ns / 60 Ohms =3D 10.5 A/ns
>
>Considering a maximum allowable swing of 75 mV on rails,=20
>
>I get max allowable GND/PWR inductance of 7 pH. Note that GND is more=
> important since the receiver terminate the line at VDD.
>
>Now the questions:
>
>1- Is there any hole with my assumptions?
>2- Should I worry about other factors than Rail collapse (crosstalk and EMI=
> excluded)
>3- Is 7 pH of total GND inductance do-able?
>4- What would you specify differently if you were me? And why?
>5- Is anyone ever pushed a 70 bits single ended interface that fast? How?
>
>Thanks for the answers,
>Steph.
>
>______________________________________________
>
>St=E9phane Tremblay
>Hardware project leader
>
>Matrox Graphics Inc.  (MGI)=20
>1025 St-Regis, Dorval (Quebec), H9P 2T4=20
>
>Telephone   : (514) 822-6300 #2930=20
>Fax         : (514) 685-7030=20
>email       : Stephane.Tremblay@xxxxxxxxxx=20
>______________________________________________
>USA address : Matrox Graphics Inc.=20
>               625 State Route 3 #B=20
>               Plattsburg, NY, USA, 12901-6530=20
>______________________________________________
>
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>


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