[SI-LIST] Re: Power Plane impedance simulation in PowerSI
- From: Larry Smith <LSMITH@xxxxxxxxxx>
- To: Jory McKinley <jory_mckinley@xxxxxxxxx>, Istvan Novak <istvan.novak@xxxxxxx>, Dan <signal.integrity2@xxxxxxxxx>
- Date: Fri, 18 Feb 2011 10:36:24 -0800
There are sophisticated tools and methodologies available in the industry to do
the analysis that Jory has suggested. But it is probably useful to do some
hand analysis to see where the problem areas are and evaluate possible
solutions. In the initial problem statement, Dan said that his target
impedance was 3 mOhms but his board impedance was 30 mOhms at his frequency of
operation (400 to 600 MHz). The good news is that the board does not have to
supply current to the FPGA in that frequency band. The FPGA core is likely to
have 500nF or more of on-die capacitance to cover the situation. At 500 MHz,
500nF is 0.64 mOhms and the impedance seen by the on-die circuits is much less
than the target impedance.
Steve correctly brought up the Z-axis inductance issue. The vertical
structures, including the PCB vias, package balls, vias and C4 bumps, are
likely sum up to 250 pH. Istvan mentioned that we get 3 mOhms from 1 pH at 500
MHz and illustrated the challenge that inductance presents. The most important
inductance in this picture is the 250 pH standing between the PCB power planes
and the die that consumes the current. Another useful hand calculation is the
frequency at which the Z-axis inductance (reactance) exceeds the target
impedance. 250 pH is 3 mOhms at 1.9 MHz. The Z-axis reactance exceeds the
target impedance at 1.9 MHz. Above that frequency, the PCB power planes will
not be able to supply current to the die at an impedance that is below the
target impedance. Hmmm. There is a corner frequency in the low MHz range
above which the PCB is not capable of improving the power integrity for the die.
This is the problem that falls into the lap of all silicon product designers
including FPGAs. It is good for system designers to use tools such as PowerSI
to analyze the situation but the results have already been determined when the
component house chose the number and pattern of power/ground balls on the
bottom of the package and the internal structure of the package that delivers
power to the die. The PCB designer can work with the stackup to determine the
PCB power via length but his/her via pattern must follow the via pattern laid
down by the component house. There is very little that can be done on the
board to improve the power integrity for the die core above a few MHz. (Other
PDNs with higher target impedances will have higher corner frequencies.)
It is up to the silicon/package component house to manage the PDN impedance in
the crucial frequency band between the frequency where the Z-axis reactance
exceeds the target impedance and the frequency where the on-die capacitance
brings the PDN impedance back down below the target impedance (the die/package
resonance band). Fortunately, we have things like on-package capacitors and
can choose package power plane and via topologies with sufficiently low
inductance to make them effective. Nevertheless, this is a very important
issue that affects both the performance and cost of silicon products.
Altera provides customer guidance for our products through our PDN Design Tool.
http://www.altera.com/technology/signal/power-distribution-network/sgl-pdn.html
For specific product families, the customer can see the effective corner
frequency where the board leaves off and the component takes over in managing
the power integrity for the die. For the low target impedance core supplies,
this is will be several MHz (FPGA customers do not need to worry about
decoupling boards at several hundred MHz). For those who are up to a
challenge, it is certainly an interesting project to use PowerSI and similar
industrial tools to analyze the power integrity of the full system. Hopefully,
your component house has already done the work for you. In any case, there is
very little that can be done on the board to correct power integrity issues
that must be managed in the package and die.
Regards,
Larry Smith
Altera Corporation
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Jory McKinley
Sent: Thursday, February 17, 2011 11:49 AM
To: Istvan Novak; Dan
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Power Plane impedance simulation in PowerSI
Hello Dan,
Try this to determine where you can make the biggest impact on your PDN
requirements. Do you have a model of the FPGA package? I assume the PDN
requirements are at the Bumps of the chip since the board effects in general
will limit you to under a couple hundred Mhz. I will go with you have some sort
of FPGA model, first make sure you have the correct decoupling my guess is that
this decoupling will be across an array of chip bumps and should be multiplied
correctly. This is where you will see the biggest impact on your PDN
frequencies of interest. You can with enough local chip capacitance swamp out
the z-direction inductance that exist not only in the board PDN but also the
package PDN. In PowerSI create ports that are open for the package model bump
and ball without any decoupling. Also, in PowerSI since you have the board in
some form create another open model of your board PDN leaving open the board
capacitance at physically/electrically the shortest paths. You will not have to
run PowerSI again until you find an optimal solution. Take the models into a
basic optimizer tool (like Genesys or equal) and sweep various combination's of
s-parameter decoupling (you also have control of local chip decoupling modeling)
and also notice the effect as you move the planar model closer to the top side
as the optimizer tool "trys" to converge on best fit.
Let me know if you are interesting in any more details.
-Jory
________________________________
From: Istvan Novak <istvan.novak@xxxxxxx>
To: Dan <signal.integrity2@xxxxxxxxx>
Cc: si-list@xxxxxxxxxxxxx
Sent: Thu, February 17, 2011 8:29:56 AM
Subject: [SI-LIST] Re: Power Plane impedance simulation in PowerSI
Dan,
Good embedded capacitance layer may help, but not to the extent that is
expected here.
We get 3mOhm impedance at 500MHz from just 1pH inductance. One bypass
capacitor
has several hundred pH loop inductance at best, say 500pH. If we pave
the back side of
the BGA field with capacitors (and not rely on thin laminates), we need
at least 500 of
them to get 1pH inductance. I assume the cumulative inductance of all of
the capacitors
in your circuit is higher than 1pH, and they are probably not all
directly in the BGA pinfield,
so the next we can rely on is the low inductance of the embedded
capacitance layer.
1mil plane separation (25.4 micrometer) comes with approximately 33pH
plane inductance.
If we wanted to get 1pH, we would need a dielectric thickness of less
than a micrometer.
Bottom line: when it comes to milliohm self impedances, the inductance
of capacitors and
planes will limit us up h frequencies we can maintain it.
Regards,
Istvan Novak
Oracle
On 2/17/2011 2:21 AM, Dan wrote:
> Hi All,
> I am simulating a big board which is 12"x!2" dimension and 44 layer stackup.
> I have FPGA in the center of the board (TOP layer). all the decoupling
> capacitors are straight below the DUT in the bottom layer. The position of
> the decaps are optimized and it has the shortest inductive path as possible.
>
> my target impedance is 3 mohms. I am simulating this board in powerSI to
> find the power plane impedance. But the impedance i obtain is around 30 m
> ohms between 400MHZ and 600 MHz which is the frequency of operation.
>
> I change all the capacitor models with the various lowESR and low ESL caps s
> parameter model available with various capacitor manufacturers. the
> impedance is not getting lowered. Since it is a very big board, i am not
> able to do quick iterations. So now i tried by cutting the DUT region and
> simulating the smal area of 4"x4". I know the impedance may not be correct.
> In the same i got a 10 m ohm impedance in the power plane. But i tried 10
> iteration with various capacitor even with the worst case ESR and ESL caps.
> but the impedance plot didnt not change.
>
> I have a good embeded PCB capacitance as well. Any comments or idea how
> to get closer to the target impedance? and why the impedance is not changing
> at all in the smaller cut model even after changing the caps. Any PowerSI
> users please post your comments or idea about this problem or the tool.
>
> Thank You
> Dan
>
>
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