[SI-LIST] Ballpark estimating of PDN requirements when not provided [was Power Plane impedance simulation in PowerSI]
- From: "alfred1520list" <alfred1520list@xxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Fri, 18 Feb 2011 11:34:14 -0800
Hi List,
Apology if the question is redundant.
While PDN design is straight forward engineering when the PDN
target requirements for the device was provided, how do one deal
with the problem when such is not available?
Can you make an order of magnitude estimate simply from the
current consumptions of the IC? long term average (second(s)),
peak current? current spectra (it might also be difficult to
measure beyond several MHz.)
Thanks for any insight.
Best Regards,
Alfred Lee
www.mds.com
----- Original Message -----
From: "Larry Smith" <LSMITH@xxxxxxxxxx>
To: "Jory McKinley" <jory_mckinley@xxxxxxxxx>; "Istvan Novak"
<istvan.novak@xxxxxxx>; "Dan" <signal.integrity2@xxxxxxxxx>
Cc: <si-list@xxxxxxxxxxxxx>
Sent: Friday, February 18, 2011 10:36 AM
Subject: [SI-LIST] Re: Power Plane impedance simulation in PowerSI
> There are sophisticated tools and methodologies available in the industry to
> do the analysis that Jory has suggested. But it is
> probably useful to do some hand analysis to see where the problem areas are
> and evaluate possible solutions. In the initial
> problem statement, Dan said that his target impedance was 3 mOhms but his
> board impedance was 30 mOhms at his frequency of
> operation (400 to 600 MHz). The good news is that the board does not have to
> supply current to the FPGA in that frequency band.
> The FPGA core is likely to have 500nF or more of on-die capacitance to cover
> the situation. At 500 MHz, 500nF is 0.64 mOhms and
> the impedance seen by the on-die circuits is much less than the target
> impedance.
>
> Steve correctly brought up the Z-axis inductance issue. The vertical
> structures, including the PCB vias, package balls, vias and
> C4 bumps, are likely sum up to 250 pH. Istvan mentioned that we get 3 mOhms
> from 1 pH at 500 MHz and illustrated the challenge
> that inductance presents. The most important inductance in this picture is
> the 250 pH standing between the PCB power planes and
> the die that consumes the current. Another useful hand calculation is the
> frequency at which the Z-axis inductance (reactance)
> exceeds the target impedance. 250 pH is 3 mOhms at 1.9 MHz. The Z-axis
> reactance exceeds the target impedance at 1.9 MHz. Above
> that frequency, the PCB power planes will not be able to supply current to
> the die at an impedance that is below the target
> impedance. Hmmm. There is a corner frequency in the low MHz range above
> which the PCB is not capable of improving the power
> integrity for the die.
>
> This is the problem that falls into the lap of all silicon product designers
> including FPGAs. It is good for system designers to
> use tools such as PowerSI to analyze the situation but the results have
> already been determined when the component house chose the
> number and pattern of power/ground balls on the bottom of the package and the
> internal structure of the package that delivers
> power to the die. The PCB designer can work with the stackup to determine
> the PCB power via length but his/her via pattern must
> follow the via pattern laid down by the component house. There is very
> little that can be done on the board to improve the power
> integrity for the die core above a few MHz. (Other PDNs with higher target
> impedances will have higher corner frequencies.)
>
> It is up to the silicon/package component house to manage the PDN impedance
> in the crucial frequency band between the frequency
> where the Z-axis reactance exceeds the target impedance and the frequency
> where the on-die capacitance brings the PDN impedance
> back down below the target impedance (the die/package resonance band).
> Fortunately, we have things like on-package capacitors and
> can choose package power plane and via topologies with sufficiently low
> inductance to make them effective. Nevertheless, this is
> a very important issue that affects both the performance and cost of silicon
> products.
>
> Altera provides customer guidance for our products through our PDN Design
> Tool.
> http://www.altera.com/technology/signal/power-distribution-network/sgl-pdn.html
> For specific product families, the customer can see the effective corner
> frequency where the board leaves off and the component
> takes over in managing the power integrity for the die. For the low target
> impedance core supplies, this is will be several MHz
> (FPGA customers do not need to worry about decoupling boards at several
> hundred MHz). For those who are up to a challenge, it is
> certainly an interesting project to use PowerSI and similar industrial tools
> to analyze the power integrity of the full system.
> Hopefully, your component house has already done the work for you. In any
> case, there is very little that can be done on the
> board to correct power integrity issues that must be managed in the package
> and die.
>
> Regards,
> Larry Smith
> Altera Corporation
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