[SI-LIST] Re: Power Plane impedance simulation in PowerSI
- From: steve weir <weirsi@xxxxxxxxxx>
- To: Dan <signal.integrity2@xxxxxxxxx>
- Date: Wed, 16 Feb 2011 23:46:09 -0800
Dan, you are suffering death from Z axis inductance. The way that I
usually address this sort of problem is to position a Vcc/Vss puddle
close to the chip mounting surface that then has a few capacitors on the
same surface as the IC. Depending on the specific device pin-outs and
number of supply rails, I will then determine whether thin dielectric
improves cost or is just necessary. Finally, I add bypass caps to meet
the final impedance requirements. The choice of capacitors depends on a
number of factors, including restrictions that the customer may place.
There is some more detail on this in my DesignCon 2009 paper available
on that is available on the ipblox web-site. My basic message is that
the more demanding the power requirements, the more likely you are to
benefit from either or both thin dielectric and low ESL capacitors.
There are two other items you should note:
1. Target impedance for a rail is only the same as required at a given
IC when one IC represents almost all the AC current load. From a PI
standpoint it is the impedance ultimately seen by each die that matters.
2. 3mOhms at the PCB implies many Vcc / Vss balls into the part. BGAs
have similar Z axis inductance limitations as PCBs. If the Z axis from
the device mounting pads into the part is limiting, changing the PCB
impedance to from something pedestrian to super low inductance won't
help much.
And a last note:
Beware of resonance issues aggravated by turning the back of the PCB,
especially a thick PCB black with bypass caps.
Steve.
Dan wrote:
> Hi All,
> I am simulating a big board which is 12"x!2" dimension and 44 layer stackup.
> I have FPGA in the center of the board (TOP layer). all the decoupling
> capacitors are straight below the DUT in the bottom layer. The position of
> the decaps are optimized and it has the shortest inductive path as possible.
>
> my target impedance is 3 mohms. I am simulating this board in powerSI to
> find the power plane impedance. But the impedance i obtain is around 30 m
> ohms between 400MHZ and 600 MHz which is the frequency of operation.
>
> I change all the capacitor models with the various lowESR and low ESL caps s
> parameter model available with various capacitor manufacturers. the
> impedance is not getting lowered. Since it is a very big board, i am not
> able to do quick iterations. So now i tried by cutting the DUT region and
> simulating the smal area of 4"x4". I know the impedance may not be correct.
> In the same i got a 10 m ohm impedance in the power plane. But i tried 10
> iteration with various capacitor even with the worst case ESR and ESL caps.
> but the impedance plot didnt not change.
>
> I have a good embeded PCB capacitance as well. Any comments or idea how
> to get closer to the target impedance? and why the impedance is not changing
> at all in the smaller cut model even after changing the caps. Any PowerSI
> users please post your comments or idea about this problem or the tool.
>
> Thank You
> Dan
>
>
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--
Steve Weir
IPBLOX, LLC
150 N. Center St. #211
Reno, NV 89501
www.ipblox.com
(775) 299-4236 Business
(866) 675-4630 Toll-free
(707) 780-1951 Fax
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