[SI-LIST] Re: PDS analysis?

  • From: Dan Smith <Dan.Smith@xxxxxxxxx>
  • To: "Bowden, Ivor" <ibowden@xxxxxxxxxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
  • Date: Fri, 28 Mar 2008 08:56:05 -0700

Ivor,

With what you described below there could be problems.  These problems woul=
d be manifested as noise ripple on your VCC planes which will eat into your=
 margins budget for Vih and Vil of your devices.  By placing only 0.1uf cap=
acitors and no other values, you have only minimized your noise on your pow=
er planes at about 10mhz.

You can never eliminate your parallel resonance but adding additional capac=
itors will lower the overall inductance of the mounting capacitors which (w=
hen intersected with your plane capacitor) will lower the impedance holes s=
omewhat and move them out higher in frequency.  But again, they will never =
be eliminated.

You should use more capacitor values for sure.

Dan

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On=
 Behalf Of Bowden, Ivor
Sent: Friday, March 28, 2008 7:24 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] PDS analysis?

Hi SI Experts,


Say you have a typical PCB with modern technology mix of CPU, DSP, DDR, GIG=
E, PCIE, etc. Say it is a multi-layer stackup in the form of GND-SIG-SIG-GN=
D sets, with the power distribution centered in the stackup as solid ground=
 plane - split power plane - split power plane - solid ground plane, using =
1oz copper and 3.5 mil dielectric. Assuming the split power planes utilize =
sufficient area to keep the point to point inductance and resistance to rea=
sonable values, and 0.1uF ceramic bypass caps are evenly placed at device p=
ins, and bulk capacitance is placed as needed, would there be reason to exp=
ect any problems, such as plane resonance, etc? If so, what would be the ob=
servable real world manifestations, in terms of circuit performance and pow=
er pins scope waveforms? Would there be significant advantage to analyzing =
this PDS, or should following this "industry standard practice" for PCB PDS=
 be sufficient to expect robust behavior?



Thanks,



Ivor Bowden

Senior Hardware Engineer

Curtiss-Wright Controls Embedded Computing

10201 Wateridge Circle

Suite 300

San Diego, CA 92121

858-452-0020 x 4405

ibowden@xxxxxxxxxxxxxxxxx




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