[SI-LIST] PDS analysis?
- From: "Bowden, Ivor" <ibowden@xxxxxxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Fri, 28 Mar 2008 07:23:43 -0700
Hi SI Experts,
Say you have a typical PCB with modern technology mix of CPU, DSP, DDR, GIGE,
PCIE, etc. Say it is a multi-layer stackup in the form of GND-SIG-SIG-GND sets,
with the power distribution centered in the stackup as solid ground plane -
split power plane - split power plane - solid ground plane, using 1oz copper
and 3.5 mil dielectric. Assuming the split power planes utilize sufficient area
to keep the point to point inductance and resistance to reasonable values, and
0.1uF ceramic bypass caps are evenly placed at device pins, and bulk
capacitance is placed as needed, would there be reason to expect any problems,
such as plane resonance, etc? If so, what would be the observable real world
manifestations, in terms of circuit performance and power pins scope waveforms?
Would there be significant advantage to analyzing this PDS, or should following
this "industry standard practice" for PCB PDS be sufficient to expect robust
behavior?
Thanks,
Ivor Bowden
Senior Hardware Engineer
Curtiss-Wright Controls Embedded Computing
10201 Wateridge Circle
Suite 300
San Diego, CA 92121
858-452-0020 x 4405
ibowden@xxxxxxxxxxxxxxxxx
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