[SI-LIST] Re: MOS cap on chip for DECOUPLING
- From: Bill.Cohen@xxxxxxxxxxxxxxxx
- To: mike_bihan@xxxxxxxxxxxx
- Date: Wed, 23 Jul 2003 10:33:35 -0400
>In CMOS technology, what's the difference between using MOS cap as VCC
decoupling in three different ways?
>
>1. NMOS --> gate to VCC, other three nodes to VSS (inversion)
This is OK. Can't isolate the ground supply from the substrate in a normal
commercial Nwell process.
>2. PMOS --> gate to VCC, other three nodes to VSS (accumulation)
This is not a good capacitor. It has a high series resistance from the Well
connection (vss) to the gate oxide.
>3. PMOS --> gate to vss, other three nodes to VCC ( inversion)
This is the best capacitor for an NWELL process. The well provides
isolation from the substrate supply. The resistance can be low providing
the gate length is less than a couple of microns. We prefer this capacitor
in applications where we need to decouple isolated power supplies. Such
applications include PLL, gigabit links, etc.
--------------------------------------------------------------
| Bill Cohen
| Toshiba America Electronic Components
| Mixed Signal Design Group
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